Embedded Artistry Framework
Embedded Systems C++ Framework
Macros
vl53l1x_registers.h File Reference
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Macros

#define VL53L1_SOFT_RESET   0x0000
 VL53L1 Register Map definitions. More...
 
#define VL53L1_I2C_SLAVE_DEVICE_ADDRESS   0x0001
 
#define VL53L1_ANA_CONFIG_VHV_REF_SEL_VDDPIX   0x0002
 
#define VL53L1_ANA_CONFIG_VHV_REF_SEL_VQUENCH   0x0003
 
#define VL53L1_ANA_CONFIG_REG_AVDD1V2_SEL   0x0004
 
#define VL53L1_ANA_CONFIG_FAST_OSC_TRIM   0x0005
 
#define VL53L1_OSC_MEASURED_FAST_OSC_FREQUENCY   0x0006
 
#define VL53L1_OSC_MEASURED_FAST_OSC_FREQUENCY_HI   0x0006
 
#define VL53L1_OSC_MEASURED_FAST_OSC_FREQUENCY_LO   0x0007
 
#define VL53L1_VHV_CONFIG_TIMEOUT_MACROP_LOOP_BOUND   0x0008
 
#define VL53L1_VHV_CONFIG_COUNT_THRESH   0x0009
 
#define VL53L1_VHV_CONFIG_OFFSET   0x000A
 
#define VL53L1_VHV_CONFIG_INIT   0x000B
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_REF_0   0x000D
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_REF_1   0x000E
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_REF_2   0x000F
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_REF_3   0x0010
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_REF_4   0x0011
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_REF_5   0x0012
 
#define VL53L1_GLOBAL_CONFIG_REF_EN_START_SELECT   0x0013
 
#define VL53L1_REF_SPAD_MAN_NUM_REQUESTED_REF_SPADS   0x0014
 
#define VL53L1_REF_SPAD_MAN_REF_LOCATION   0x0015
 
#define VL53L1_ALGO_CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS   0x0016
 
#define VL53L1_ALGO_CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS_HI   0x0016
 
#define VL53L1_ALGO_CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS_LO   0x0017
 
#define VL53L1_ALGO_CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS   0x0018
 
#define VL53L1_ALGO_CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS_HI   0x0018
 
#define VL53L1_ALGO_CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS_LO   0x0019
 
#define VL53L1_ALGO_CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS   0x001A
 
#define VL53L1_ALGO_CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS_HI   0x001A
 
#define VL53L1_ALGO_CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS_LO   0x001B
 
#define VL53L1_REF_SPAD_CHAR_TOTAL_RATE_TARGET_MCPS   0x001C
 
#define VL53L1_REF_SPAD_CHAR_TOTAL_RATE_TARGET_MCPS_HI   0x001C
 
#define VL53L1_REF_SPAD_CHAR_TOTAL_RATE_TARGET_MCPS_LO   0x001D
 
#define VL53L1_ALGO_PART_TO_PART_RANGE_OFFSET_MM   0x001E
 
#define VL53L1_ALGO_PART_TO_PART_RANGE_OFFSET_MM_HI   0x001E
 
#define VL53L1_ALGO_PART_TO_PART_RANGE_OFFSET_MM_LO   0x001F
 
#define VL53L1_MM_CONFIG_INNER_OFFSET_MM   0x0020
 
#define VL53L1_MM_CONFIG_INNER_OFFSET_MM_HI   0x0020
 
#define VL53L1_MM_CONFIG_INNER_OFFSET_MM_LO   0x0021
 
#define VL53L1_MM_CONFIG_OUTER_OFFSET_MM   0x0022
 
#define VL53L1_MM_CONFIG_OUTER_OFFSET_MM_HI   0x0022
 
#define VL53L1_MM_CONFIG_OUTER_OFFSET_MM_LO   0x0023
 
#define VL53L1_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS   0x0024
 
#define VL53L1_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_HI   0x0024
 
#define VL53L1_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_LO   0x0025
 
#define VL53L1_DEBUG_CTRL   0x0026
 
#define VL53L1_TEST_MODE_CTRL   0x0027
 
#define VL53L1_CLK_GATING_CTRL   0x0028
 
#define VL53L1_NVM_BIST_CTRL   0x0029
 
#define VL53L1_NVM_BIST_NUM_NVM_WORDS   0x002A
 
#define VL53L1_NVM_BIST_START_ADDRESS   0x002B
 
#define VL53L1_HOST_IF_STATUS   0x002C
 
#define VL53L1_PAD_I2C_HV_CONFIG   0x002D
 
#define VL53L1_PAD_I2C_HV_EXTSUP_CONFIG   0x002E
 
#define VL53L1_GPIO_HV_PAD_CTRL   0x002F
 
#define VL53L1_GPIO_HV_MUX_CTRL   0x0030
 
#define VL53L1_GPIO_TIO_HV_STATUS   0x0031
 
#define VL53L1_GPIO_FIO_HV_STATUS   0x0032
 
#define VL53L1_ANA_CONFIG_SPAD_SEL_PSWIDTH   0x0033
 
#define VL53L1_ANA_CONFIG_VCSEL_PULSE_WIDTH_OFFSET   0x0034
 
#define VL53L1_ANA_CONFIG_FAST_OSC_CONFIG_CTRL   0x0035
 
#define VL53L1_SIGMA_ESTIMATOR_EFFECTIVE_PULSE_WIDTH_NS   0x0036
 
#define VL53L1_SIGMA_ESTIMATOR_EFFECTIVE_AMBIENT_WIDTH_NS   0x0037
 
#define VL53L1_SIGMA_ESTIMATOR_SIGMA_REF_MM   0x0038
 
#define VL53L1_ALGO_CROSSTALK_COMPENSATION_VALID_HEIGHT_MM   0x0039
 
#define VL53L1_SPARE_HOST_CONFIG_STATIC_CONFIG_SPARE_0   0x003A
 
#define VL53L1_SPARE_HOST_CONFIG_STATIC_CONFIG_SPARE_1   0x003B
 
#define VL53L1_ALGO_RANGE_IGNORE_THRESHOLD_MCPS   0x003C
 
#define VL53L1_ALGO_RANGE_IGNORE_THRESHOLD_MCPS_HI   0x003C
 
#define VL53L1_ALGO_RANGE_IGNORE_THRESHOLD_MCPS_LO   0x003D
 
#define VL53L1_ALGO_RANGE_IGNORE_VALID_HEIGHT_MM   0x003E
 
#define VL53L1_ALGO_RANGE_MIN_CLIP   0x003F
 
#define VL53L1_ALGO_CONSISTENCY_CHECK_TOLERANCE   0x0040
 
#define VL53L1_SPARE_HOST_CONFIG_STATIC_CONFIG_SPARE_2   0x0041
 
#define VL53L1_SD_CONFIG_RESET_STAGES_MSB   0x0042
 
#define VL53L1_SD_CONFIG_RESET_STAGES_LSB   0x0043
 
#define VL53L1_GPH_CONFIG_STREAM_COUNT_UPDATE_VALUE   0x0044
 
#define VL53L1_GLOBAL_CONFIG_STREAM_DIVIDER   0x0045
 
#define VL53L1_SYSTEM_INTERRUPT_CONFIG_GPIO   0x0046
 
#define VL53L1_CAL_CONFIG_VCSEL_START   0x0047
 
#define VL53L1_CAL_CONFIG_REPEAT_RATE   0x0048
 
#define VL53L1_CAL_CONFIG_REPEAT_RATE_HI   0x0048
 
#define VL53L1_CAL_CONFIG_REPEAT_RATE_LO   0x0049
 
#define VL53L1_GLOBAL_CONFIG_VCSEL_WIDTH   0x004A
 
#define VL53L1_PHASECAL_CONFIG_TIMEOUT_MACROP   0x004B
 
#define VL53L1_PHASECAL_CONFIG_TARGET   0x004C
 
#define VL53L1_PHASECAL_CONFIG_OVERRIDE   0x004D
 
#define VL53L1_DSS_CONFIG_ROI_MODE_CONTROL   0x004F
 
#define VL53L1_SYSTEM_THRESH_RATE_HIGH   0x0050
 
#define VL53L1_SYSTEM_THRESH_RATE_HIGH_HI   0x0050
 
#define VL53L1_SYSTEM_THRESH_RATE_HIGH_LO   0x0051
 
#define VL53L1_SYSTEM_THRESH_RATE_LOW   0x0052
 
#define VL53L1_SYSTEM_THRESH_RATE_LOW_HI   0x0052
 
#define VL53L1_SYSTEM_THRESH_RATE_LOW_LO   0x0053
 
#define VL53L1_DSS_CONFIG_MANUAL_EFFECTIVE_SPADS_SELECT   0x0054
 
#define VL53L1_DSS_CONFIG_MANUAL_EFFECTIVE_SPADS_SELECT_HI   0x0054
 
#define VL53L1_DSS_CONFIG_MANUAL_EFFECTIVE_SPADS_SELECT_LO   0x0055
 
#define VL53L1_DSS_CONFIG_MANUAL_BLOCK_SELECT   0x0056
 
#define VL53L1_DSS_CONFIG_APERTURE_ATTENUATION   0x0057
 
#define VL53L1_DSS_CONFIG_MAX_SPADS_LIMIT   0x0058
 
#define VL53L1_DSS_CONFIG_MIN_SPADS_LIMIT   0x0059
 
#define VL53L1_MM_CONFIG_TIMEOUT_MACROP_A_HI   0x005A
 
#define VL53L1_MM_CONFIG_TIMEOUT_MACROP_A_LO   0x005B
 
#define VL53L1_MM_CONFIG_TIMEOUT_MACROP_B_HI   0x005C
 
#define VL53L1_MM_CONFIG_TIMEOUT_MACROP_B_LO   0x005D
 
#define VL53L1_RANGE_CONFIG_TIMEOUT_MACROP_A_HI   0x005E
 
#define VL53L1_RANGE_CONFIG_TIMEOUT_MACROP_A_LO   0x005F
 
#define VL53L1_RANGE_CONFIG_VCSEL_PERIOD_A   0x0060
 
#define VL53L1_RANGE_CONFIG_TIMEOUT_MACROP_B_HI   0x0061
 
#define VL53L1_RANGE_CONFIG_TIMEOUT_MACROP_B_LO   0x0062
 
#define VL53L1_RANGE_CONFIG_VCSEL_PERIOD_B   0x0063
 
#define VL53L1_RANGE_CONFIG_SIGMA_THRESH   0x0064
 
#define VL53L1_RANGE_CONFIG_SIGMA_THRESH_HI   0x0064
 
#define VL53L1_RANGE_CONFIG_SIGMA_THRESH_LO   0x0065
 
#define VL53L1_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT_MCPS   0x0066
 
#define VL53L1_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI   0x0066
 
#define VL53L1_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO   0x0067
 
#define VL53L1_RANGE_CONFIG_VALID_PHASE_LOW   0x0068
 
#define VL53L1_RANGE_CONFIG_VALID_PHASE_HIGH   0x0069
 
#define VL53L1_SYSTEM_INTERMEASUREMENT_PERIOD   0x006C
 
#define VL53L1_SYSTEM_INTERMEASUREMENT_PERIOD_3   0x006C
 
#define VL53L1_SYSTEM_INTERMEASUREMENT_PERIOD_2   0x006D
 
#define VL53L1_SYSTEM_INTERMEASUREMENT_PERIOD_1   0x006E
 
#define VL53L1_SYSTEM_INTERMEASUREMENT_PERIOD_0   0x006F
 
#define VL53L1_SYSTEM_FRACTIONAL_ENABLE   0x0070
 
#define VL53L1_SYSTEM_GROUPED_PARAMETER_HOLD_0   0x0071
 
#define VL53L1_SYSTEM_THRESH_HIGH   0x0072
 
#define VL53L1_SYSTEM_THRESH_HIGH_HI   0x0072
 
#define VL53L1_SYSTEM_THRESH_HIGH_LO   0x0073
 
#define VL53L1_SYSTEM_THRESH_LOW   0x0074
 
#define VL53L1_SYSTEM_THRESH_LOW_HI   0x0074
 
#define VL53L1_SYSTEM_THRESH_LOW_LO   0x0075
 
#define VL53L1_SYSTEM_ENABLE_XTALK_PER_QUADRANT   0x0076
 
#define VL53L1_SYSTEM_SEED_CONFIG   0x0077
 
#define VL53L1_SD_CONFIG_WOI_SD0   0x0078
 
#define VL53L1_SD_CONFIG_WOI_SD1   0x0079
 
#define VL53L1_SD_CONFIG_INITIAL_PHASE_SD0   0x007A
 
#define VL53L1_SD_CONFIG_INITIAL_PHASE_SD1   0x007B
 
#define VL53L1_SYSTEM_GROUPED_PARAMETER_HOLD_1   0x007C
 
#define VL53L1_SD_CONFIG_FIRST_ORDER_SELECT   0x007D
 
#define VL53L1_SD_CONFIG_QUANTIFIER   0x007E
 
#define VL53L1_ROI_CONFIG_USER_ROI_CENTRE_SPAD   0x007F
 
#define VL53L1_ROI_CONFIG_USER_ROI_REQUESTED_GLOBAL_XY_SIZE   0x0080
 
#define VL53L1_SYSTEM_SEQUENCE_CONFIG   0x0081
 
#define VL53L1_SYSTEM_GROUPED_PARAMETER_HOLD   0x0082
 
#define VL53L1_POWER_MANAGEMENT_GO1_POWER_FORCE   0x0083
 
#define VL53L1_SYSTEM_STREAM_COUNT_CTRL   0x0084
 
#define VL53L1_FIRMWARE_ENABLE   0x0085
 
#define VL53L1_SYSTEM_INTERRUPT_CLEAR   0x0086
 
#define VL53L1_SYSTEM_MODE_START   0x0087
 
#define VL53L1_RESULT_INTERRUPT_STATUS   0x0088
 
#define VL53L1_RESULT_RANGE_STATUS   0x0089
 
#define VL53L1_RESULT_REPORT_STATUS   0x008A
 
#define VL53L1_RESULT_STREAM_COUNT   0x008B
 
#define VL53L1_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0   0x008C
 
#define VL53L1_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI   0x008C
 
#define VL53L1_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO   0x008D
 
#define VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0   0x008E
 
#define VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI   0x008E
 
#define VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO   0x008F
 
#define VL53L1_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0   0x0090
 
#define VL53L1_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0_HI   0x0090
 
#define VL53L1_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0_LO   0x0091
 
#define VL53L1_RESULT_SIGMA_SD0   0x0092
 
#define VL53L1_RESULT_SIGMA_SD0_HI   0x0092
 
#define VL53L1_RESULT_SIGMA_SD0_LO   0x0093
 
#define VL53L1_RESULT_PHASE_SD0   0x0094
 
#define VL53L1_RESULT_PHASE_SD0_HI   0x0094
 
#define VL53L1_RESULT_PHASE_SD0_LO   0x0095
 
#define VL53L1_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0   0x0096
 
#define VL53L1_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI   0x0096
 
#define VL53L1_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO   0x0097
 
#define VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0   0x0098
 
#define VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI   0x0098
 
#define VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO   0x0099
 
#define VL53L1_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0   0x009A
 
#define VL53L1_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI   0x009A
 
#define VL53L1_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO   0x009B
 
#define VL53L1_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0   0x009C
 
#define VL53L1_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI   0x009C
 
#define VL53L1_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO   0x009D
 
#define VL53L1_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0   0x009E
 
#define VL53L1_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI   0x009E
 
#define VL53L1_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO   0x009F
 
#define VL53L1_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1   0x00A0
 
#define VL53L1_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI   0x00A0
 
#define VL53L1_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO   0x00A1
 
#define VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1   0x00A2
 
#define VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI   0x00A2
 
#define VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO   0x00A3
 
#define VL53L1_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1   0x00A4
 
#define VL53L1_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1_HI   0x00A4
 
#define VL53L1_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1_LO   0x00A5
 
#define VL53L1_RESULT_SIGMA_SD1   0x00A6
 
#define VL53L1_RESULT_SIGMA_SD1_HI   0x00A6
 
#define VL53L1_RESULT_SIGMA_SD1_LO   0x00A7
 
#define VL53L1_RESULT_PHASE_SD1   0x00A8
 
#define VL53L1_RESULT_PHASE_SD1_HI   0x00A8
 
#define VL53L1_RESULT_PHASE_SD1_LO   0x00A9
 
#define VL53L1_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1   0x00AA
 
#define VL53L1_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI   0x00AA
 
#define VL53L1_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO   0x00AB
 
#define VL53L1_RESULT_SPARE_0_SD1   0x00AC
 
#define VL53L1_RESULT_SPARE_0_SD1_HI   0x00AC
 
#define VL53L1_RESULT_SPARE_0_SD1_LO   0x00AD
 
#define VL53L1_RESULT_SPARE_1_SD1   0x00AE
 
#define VL53L1_RESULT_SPARE_1_SD1_HI   0x00AE
 
#define VL53L1_RESULT_SPARE_1_SD1_LO   0x00AF
 
#define VL53L1_RESULT_SPARE_2_SD1   0x00B0
 
#define VL53L1_RESULT_SPARE_2_SD1_HI   0x00B0
 
#define VL53L1_RESULT_SPARE_2_SD1_LO   0x00B1
 
#define VL53L1_RESULT_SPARE_3_SD1   0x00B2
 
#define VL53L1_RESULT_THRESH_INFO   0x00B3
 
#define VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0   0x00B4
 
#define VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_3   0x00B4
 
#define VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_2   0x00B5
 
#define VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_1   0x00B6
 
#define VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_0   0x00B7
 
#define VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0   0x00B8
 
#define VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_3   0x00B8
 
#define VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_2   0x00B9
 
#define VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_1   0x00BA
 
#define VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_0   0x00BB
 
#define VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0   0x00BC
 
#define VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_3   0x00BC
 
#define VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_2   0x00BD
 
#define VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_1   0x00BE
 
#define VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_0   0x00BF
 
#define VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0   0x00C0
 
#define VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_3   0x00C0
 
#define VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_2   0x00C1
 
#define VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_1   0x00C2
 
#define VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_0   0x00C3
 
#define VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1   0x00C4
 
#define VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_3   0x00C4
 
#define VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_2   0x00C5
 
#define VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_1   0x00C6
 
#define VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_0   0x00C7
 
#define VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1   0x00C8
 
#define VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_3   0x00C8
 
#define VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_2   0x00C9
 
#define VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_1   0x00CA
 
#define VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_0   0x00CB
 
#define VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1   0x00CC
 
#define VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_3   0x00CC
 
#define VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_2   0x00CD
 
#define VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_1   0x00CE
 
#define VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_0   0x00CF
 
#define VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1   0x00D0
 
#define VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_3   0x00D0
 
#define VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_2   0x00D1
 
#define VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_1   0x00D2
 
#define VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_0   0x00D3
 
#define VL53L1_RESULT_CORE_SPARE_0   0x00D4
 
#define VL53L1_PHASECAL_RESULT_REFERENCE_PHASE   0x00D6
 
#define VL53L1_PHASECAL_RESULT_REFERENCE_PHASE_HI   0x00D6
 
#define VL53L1_PHASECAL_RESULT_REFERENCE_PHASE_LO   0x00D7
 
#define VL53L1_PHASECAL_RESULT_VCSEL_START   0x00D8
 
#define VL53L1_REF_SPAD_CHAR_RESULT_NUM_ACTUAL_REF_SPADS   0x00D9
 
#define VL53L1_REF_SPAD_CHAR_RESULT_REF_LOCATION   0x00DA
 
#define VL53L1_VHV_RESULT_COLDBOOT_STATUS   0x00DB
 
#define VL53L1_VHV_RESULT_SEARCH_RESULT   0x00DC
 
#define VL53L1_VHV_RESULT_LATEST_SETTING   0x00DD
 
#define VL53L1_RESULT_OSC_CALIBRATE_VAL   0x00DE
 
#define VL53L1_RESULT_OSC_CALIBRATE_VAL_HI   0x00DE
 
#define VL53L1_RESULT_OSC_CALIBRATE_VAL_LO   0x00DF
 
#define VL53L1_ANA_CONFIG_POWERDOWN_GO1   0x00E0
 
#define VL53L1_ANA_CONFIG_REF_BG_CTRL   0x00E1
 
#define VL53L1_ANA_CONFIG_REGDVDD1V2_CTRL   0x00E2
 
#define VL53L1_ANA_CONFIG_OSC_SLOW_CTRL   0x00E3
 
#define VL53L1_TEST_MODE_STATUS   0x00E4
 
#define VL53L1_FIRMWARE_SYSTEM_STATUS   0x00E5
 
#define VL53L1_FIRMWARE_MODE_STATUS   0x00E6
 
#define VL53L1_FIRMWARE_SECONDARY_MODE_STATUS   0x00E7
 
#define VL53L1_FIRMWARE_CAL_REPEAT_RATE_COUNTER   0x00E8
 
#define VL53L1_FIRMWARE_CAL_REPEAT_RATE_COUNTER_HI   0x00E8
 
#define VL53L1_FIRMWARE_CAL_REPEAT_RATE_COUNTER_LO   0x00E9
 
#define VL53L1_FIRMWARE_HISTOGRAM_BIN   0x00EA
 
#define VL53L1_GPH_SYSTEM_THRESH_HIGH   0x00EC
 
#define VL53L1_GPH_SYSTEM_THRESH_HIGH_HI   0x00EC
 
#define VL53L1_GPH_SYSTEM_THRESH_HIGH_LO   0x00ED
 
#define VL53L1_GPH_SYSTEM_THRESH_LOW   0x00EE
 
#define VL53L1_GPH_SYSTEM_THRESH_LOW_HI   0x00EE
 
#define VL53L1_GPH_SYSTEM_THRESH_LOW_LO   0x00EF
 
#define VL53L1_GPH_SYSTEM_ENABLE_XTALK_PER_QUADRANT   0x00F0
 
#define VL53L1_GPH_SPARE_0   0x00F1
 
#define VL53L1_GPH_SD_CONFIG_WOI_SD0   0x00F2
 
#define VL53L1_GPH_SD_CONFIG_WOI_SD1   0x00F3
 
#define VL53L1_GPH_SD_CONFIG_INITIAL_PHASE_SD0   0x00F4
 
#define VL53L1_GPH_SD_CONFIG_INITIAL_PHASE_SD1   0x00F5
 
#define VL53L1_GPH_SD_CONFIG_FIRST_ORDER_SELECT   0x00F6
 
#define VL53L1_GPH_SD_CONFIG_QUANTIFIER   0x00F7
 
#define VL53L1_GPH_ROI_CONFIG_USER_ROI_CENTRE_SPAD   0x00F8
 
#define VL53L1_GPH_ROI_CONFIG_USER_ROI_REQUESTED_GLOBAL_XY_SIZE   0x00F9
 
#define VL53L1_GPH_SYSTEM_SEQUENCE_CONFIG   0x00FA
 
#define VL53L1_GPH_GPH_ID   0x00FB
 
#define VL53L1_SYSTEM_INTERRUPT_SET   0x00FC
 
#define VL53L1_INTERRUPT_MANAGER_ENABLES   0x00FD
 
#define VL53L1_INTERRUPT_MANAGER_CLEAR   0x00FE
 
#define VL53L1_INTERRUPT_MANAGER_STATUS   0x00FF
 
#define VL53L1_MCU_TO_HOST_BANK_WR_ACCESS_EN   0x0100
 
#define VL53L1_POWER_MANAGEMENT_GO1_RESET_STATUS   0x0101
 
#define VL53L1_PAD_STARTUP_MODE_VALUE_RO   0x0102
 
#define VL53L1_PAD_STARTUP_MODE_VALUE_CTRL   0x0103
 
#define VL53L1_PLL_PERIOD_US   0x0104
 
#define VL53L1_PLL_PERIOD_US_3   0x0104
 
#define VL53L1_PLL_PERIOD_US_2   0x0105
 
#define VL53L1_PLL_PERIOD_US_1   0x0106
 
#define VL53L1_PLL_PERIOD_US_0   0x0107
 
#define VL53L1_INTERRUPT_SCHEDULER_DATA_OUT   0x0108
 
#define VL53L1_INTERRUPT_SCHEDULER_DATA_OUT_3   0x0108
 
#define VL53L1_INTERRUPT_SCHEDULER_DATA_OUT_2   0x0109
 
#define VL53L1_INTERRUPT_SCHEDULER_DATA_OUT_1   0x010A
 
#define VL53L1_INTERRUPT_SCHEDULER_DATA_OUT_0   0x010B
 
#define VL53L1_NVM_BIST_COMPLETE   0x010C
 
#define VL53L1_NVM_BIST_STATUS   0x010D
 
#define VL53L1_IDENTIFICATION_MODEL_ID   0x010F
 
#define VL53L1_IDENTIFICATION_MODULE_TYPE   0x0110
 
#define VL53L1_IDENTIFICATION_REVISION_ID   0x0111
 
#define VL53L1_IDENTIFICATION_MODULE_ID   0x0112
 
#define VL53L1_IDENTIFICATION_MODULE_ID_HI   0x0112
 
#define VL53L1_IDENTIFICATION_MODULE_ID_LO   0x0113
 
#define VL53L1_ANA_CONFIG_FAST_OSC_TRIM_MAX   0x0114
 
#define VL53L1_ANA_CONFIG_FAST_OSC_FREQ_SET   0x0115
 
#define VL53L1_ANA_CONFIG_VCSEL_TRIM   0x0116
 
#define VL53L1_ANA_CONFIG_VCSEL_SELION   0x0117
 
#define VL53L1_ANA_CONFIG_VCSEL_SELION_MAX   0x0118
 
#define VL53L1_PROTECTED_LASER_SAFETY_LOCK_BIT   0x0119
 
#define VL53L1_LASER_SAFETY_KEY   0x011A
 
#define VL53L1_LASER_SAFETY_KEY_RO   0x011B
 
#define VL53L1_LASER_SAFETY_CLIP   0x011C
 
#define VL53L1_LASER_SAFETY_MULT   0x011D
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_0   0x011E
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_1   0x011F
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_2   0x0120
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_3   0x0121
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_4   0x0122
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_5   0x0123
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_6   0x0124
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_7   0x0125
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_8   0x0126
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_9   0x0127
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_10   0x0128
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_11   0x0129
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_12   0x012A
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_13   0x012B
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_14   0x012C
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_15   0x012D
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_16   0x012E
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_17   0x012F
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_18   0x0130
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_19   0x0131
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_20   0x0132
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_21   0x0133
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_22   0x0134
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_23   0x0135
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_24   0x0136
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_25   0x0137
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_26   0x0138
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_27   0x0139
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_28   0x013A
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_29   0x013B
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_30   0x013C
 
#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_31   0x013D
 
#define VL53L1_ROI_CONFIG_MODE_ROI_CENTRE_SPAD   0x013E
 
#define VL53L1_ROI_CONFIG_MODE_ROI_XY_SIZE   0x013F
 
#define VL53L1_GO2_HOST_BANK_ACCESS_OVERRIDE   0x0300
 
#define VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLICAND   0x0400
 
#define VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLICAND_3   0x0400
 
#define VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLICAND_2   0x0401
 
#define VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLICAND_1   0x0402
 
#define VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLICAND_0   0x0403
 
#define VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLIER   0x0404
 
#define VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLIER_3   0x0404
 
#define VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLIER_2   0x0405
 
#define VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLIER_1   0x0406
 
#define VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLIER_0   0x0407
 
#define VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_HI   0x0408
 
#define VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_HI_3   0x0408
 
#define VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_HI_2   0x0409
 
#define VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_HI_1   0x040A
 
#define VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_HI_0   0x040B
 
#define VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_LO   0x040C
 
#define VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_LO_3   0x040C
 
#define VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_LO_2   0x040D
 
#define VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_LO_1   0x040E
 
#define VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_LO_0   0x040F
 
#define VL53L1_MCU_UTIL_MULTIPLIER_START   0x0410
 
#define VL53L1_MCU_UTIL_MULTIPLIER_STATUS   0x0411
 
#define VL53L1_MCU_UTIL_DIVIDER_START   0x0412
 
#define VL53L1_MCU_UTIL_DIVIDER_STATUS   0x0413
 
#define VL53L1_MCU_UTIL_DIVIDER_DIVIDEND   0x0414
 
#define VL53L1_MCU_UTIL_DIVIDER_DIVIDEND_3   0x0414
 
#define VL53L1_MCU_UTIL_DIVIDER_DIVIDEND_2   0x0415
 
#define VL53L1_MCU_UTIL_DIVIDER_DIVIDEND_1   0x0416
 
#define VL53L1_MCU_UTIL_DIVIDER_DIVIDEND_0   0x0417
 
#define VL53L1_MCU_UTIL_DIVIDER_DIVISOR   0x0418
 
#define VL53L1_MCU_UTIL_DIVIDER_DIVISOR_3   0x0418
 
#define VL53L1_MCU_UTIL_DIVIDER_DIVISOR_2   0x0419
 
#define VL53L1_MCU_UTIL_DIVIDER_DIVISOR_1   0x041A
 
#define VL53L1_MCU_UTIL_DIVIDER_DIVISOR_0   0x041B
 
#define VL53L1_MCU_UTIL_DIVIDER_QUOTIENT   0x041C
 
#define VL53L1_MCU_UTIL_DIVIDER_QUOTIENT_3   0x041C
 
#define VL53L1_MCU_UTIL_DIVIDER_QUOTIENT_2   0x041D
 
#define VL53L1_MCU_UTIL_DIVIDER_QUOTIENT_1   0x041E
 
#define VL53L1_MCU_UTIL_DIVIDER_QUOTIENT_0   0x041F
 
#define VL53L1_TIMER0_VALUE_IN   0x0420
 
#define VL53L1_TIMER0_VALUE_IN_3   0x0420
 
#define VL53L1_TIMER0_VALUE_IN_2   0x0421
 
#define VL53L1_TIMER0_VALUE_IN_1   0x0422
 
#define VL53L1_TIMER0_VALUE_IN_0   0x0423
 
#define VL53L1_TIMER1_VALUE_IN   0x0424
 
#define VL53L1_TIMER1_VALUE_IN_3   0x0424
 
#define VL53L1_TIMER1_VALUE_IN_2   0x0425
 
#define VL53L1_TIMER1_VALUE_IN_1   0x0426
 
#define VL53L1_TIMER1_VALUE_IN_0   0x0427
 
#define VL53L1_TIMER0_CTRL   0x0428
 
#define VL53L1_TIMER1_CTRL   0x0429
 
#define VL53L1_MCU_GENERAL_PURPOSE_GP_0   0x042C
 
#define VL53L1_MCU_GENERAL_PURPOSE_GP_1   0x042D
 
#define VL53L1_MCU_GENERAL_PURPOSE_GP_2   0x042E
 
#define VL53L1_MCU_GENERAL_PURPOSE_GP_3   0x042F
 
#define VL53L1_MCU_RANGE_CALC_CONFIG   0x0430
 
#define VL53L1_MCU_RANGE_CALC_OFFSET_CORRECTED_RANGE   0x0432
 
#define VL53L1_MCU_RANGE_CALC_OFFSET_CORRECTED_RANGE_HI   0x0432
 
#define VL53L1_MCU_RANGE_CALC_OFFSET_CORRECTED_RANGE_LO   0x0433
 
#define VL53L1_MCU_RANGE_CALC_SPARE_4   0x0434
 
#define VL53L1_MCU_RANGE_CALC_SPARE_4_3   0x0434
 
#define VL53L1_MCU_RANGE_CALC_SPARE_4_2   0x0435
 
#define VL53L1_MCU_RANGE_CALC_SPARE_4_1   0x0436
 
#define VL53L1_MCU_RANGE_CALC_SPARE_4_0   0x0437
 
#define VL53L1_MCU_RANGE_CALC_AMBIENT_DURATION_PRE_CALC   0x0438
 
#define VL53L1_MCU_RANGE_CALC_AMBIENT_DURATION_PRE_CALC_HI   0x0438
 
#define VL53L1_MCU_RANGE_CALC_AMBIENT_DURATION_PRE_CALC_LO   0x0439
 
#define VL53L1_MCU_RANGE_CALC_ALGO_VCSEL_PERIOD   0x043C
 
#define VL53L1_MCU_RANGE_CALC_SPARE_5   0x043D
 
#define VL53L1_MCU_RANGE_CALC_ALGO_TOTAL_PERIODS   0x043E
 
#define VL53L1_MCU_RANGE_CALC_ALGO_TOTAL_PERIODS_HI   0x043E
 
#define VL53L1_MCU_RANGE_CALC_ALGO_TOTAL_PERIODS_LO   0x043F
 
#define VL53L1_MCU_RANGE_CALC_ALGO_ACCUM_PHASE   0x0440
 
#define VL53L1_MCU_RANGE_CALC_ALGO_ACCUM_PHASE_3   0x0440
 
#define VL53L1_MCU_RANGE_CALC_ALGO_ACCUM_PHASE_2   0x0441
 
#define VL53L1_MCU_RANGE_CALC_ALGO_ACCUM_PHASE_1   0x0442
 
#define VL53L1_MCU_RANGE_CALC_ALGO_ACCUM_PHASE_0   0x0443
 
#define VL53L1_MCU_RANGE_CALC_ALGO_SIGNAL_EVENTS   0x0444
 
#define VL53L1_MCU_RANGE_CALC_ALGO_SIGNAL_EVENTS_3   0x0444
 
#define VL53L1_MCU_RANGE_CALC_ALGO_SIGNAL_EVENTS_2   0x0445
 
#define VL53L1_MCU_RANGE_CALC_ALGO_SIGNAL_EVENTS_1   0x0446
 
#define VL53L1_MCU_RANGE_CALC_ALGO_SIGNAL_EVENTS_0   0x0447
 
#define VL53L1_MCU_RANGE_CALC_ALGO_AMBIENT_EVENTS   0x0448
 
#define VL53L1_MCU_RANGE_CALC_ALGO_AMBIENT_EVENTS_3   0x0448
 
#define VL53L1_MCU_RANGE_CALC_ALGO_AMBIENT_EVENTS_2   0x0449
 
#define VL53L1_MCU_RANGE_CALC_ALGO_AMBIENT_EVENTS_1   0x044A
 
#define VL53L1_MCU_RANGE_CALC_ALGO_AMBIENT_EVENTS_0   0x044B
 
#define VL53L1_MCU_RANGE_CALC_SPARE_6   0x044C
 
#define VL53L1_MCU_RANGE_CALC_SPARE_6_HI   0x044C
 
#define VL53L1_MCU_RANGE_CALC_SPARE_6_LO   0x044D
 
#define VL53L1_MCU_RANGE_CALC_ALGO_ADJUST_VCSEL_PERIOD   0x044E
 
#define VL53L1_MCU_RANGE_CALC_ALGO_ADJUST_VCSEL_PERIOD_HI   0x044E
 
#define VL53L1_MCU_RANGE_CALC_ALGO_ADJUST_VCSEL_PERIOD_LO   0x044F
 
#define VL53L1_MCU_RANGE_CALC_NUM_SPADS   0x0450
 
#define VL53L1_MCU_RANGE_CALC_NUM_SPADS_HI   0x0450
 
#define VL53L1_MCU_RANGE_CALC_NUM_SPADS_LO   0x0451
 
#define VL53L1_MCU_RANGE_CALC_PHASE_OUTPUT   0x0452
 
#define VL53L1_MCU_RANGE_CALC_PHASE_OUTPUT_HI   0x0452
 
#define VL53L1_MCU_RANGE_CALC_PHASE_OUTPUT_LO   0x0453
 
#define VL53L1_MCU_RANGE_CALC_RATE_PER_SPAD_MCPS   0x0454
 
#define VL53L1_MCU_RANGE_CALC_RATE_PER_SPAD_MCPS_3   0x0454
 
#define VL53L1_MCU_RANGE_CALC_RATE_PER_SPAD_MCPS_2   0x0455
 
#define VL53L1_MCU_RANGE_CALC_RATE_PER_SPAD_MCPS_1   0x0456
 
#define VL53L1_MCU_RANGE_CALC_RATE_PER_SPAD_MCPS_0   0x0457
 
#define VL53L1_MCU_RANGE_CALC_SPARE_7   0x0458
 
#define VL53L1_MCU_RANGE_CALC_SPARE_8   0x0459
 
#define VL53L1_MCU_RANGE_CALC_PEAK_SIGNAL_RATE_MCPS   0x045A
 
#define VL53L1_MCU_RANGE_CALC_PEAK_SIGNAL_RATE_MCPS_HI   0x045A
 
#define VL53L1_MCU_RANGE_CALC_PEAK_SIGNAL_RATE_MCPS_LO   0x045B
 
#define VL53L1_MCU_RANGE_CALC_AVG_SIGNAL_RATE_MCPS   0x045C
 
#define VL53L1_MCU_RANGE_CALC_AVG_SIGNAL_RATE_MCPS_HI   0x045C
 
#define VL53L1_MCU_RANGE_CALC_AVG_SIGNAL_RATE_MCPS_LO   0x045D
 
#define VL53L1_MCU_RANGE_CALC_AMBIENT_RATE_MCPS   0x045E
 
#define VL53L1_MCU_RANGE_CALC_AMBIENT_RATE_MCPS_HI   0x045E
 
#define VL53L1_MCU_RANGE_CALC_AMBIENT_RATE_MCPS_LO   0x045F
 
#define VL53L1_MCU_RANGE_CALC_XTALK   0x0460
 
#define VL53L1_MCU_RANGE_CALC_XTALK_HI   0x0460
 
#define VL53L1_MCU_RANGE_CALC_XTALK_LO   0x0461
 
#define VL53L1_MCU_RANGE_CALC_CALC_STATUS   0x0462
 
#define VL53L1_MCU_RANGE_CALC_DEBUG   0x0463
 
#define VL53L1_MCU_RANGE_CALC_PEAK_SIGNAL_RATE_XTALK_CORR_MCPS   0x0464
 
#define VL53L1_MCU_RANGE_CALC_PEAK_SIGNAL_RATE_XTALK_CORR_MCPS_HI   0x0464
 
#define VL53L1_MCU_RANGE_CALC_PEAK_SIGNAL_RATE_XTALK_CORR_MCPS_LO   0x0465
 
#define VL53L1_MCU_RANGE_CALC_SPARE_0   0x0468
 
#define VL53L1_MCU_RANGE_CALC_SPARE_1   0x0469
 
#define VL53L1_MCU_RANGE_CALC_SPARE_2   0x046A
 
#define VL53L1_MCU_RANGE_CALC_SPARE_3   0x046B
 
#define VL53L1_PATCH_CTRL   0x0470
 
#define VL53L1_PATCH_JMP_ENABLES   0x0472
 
#define VL53L1_PATCH_JMP_ENABLES_HI   0x0472
 
#define VL53L1_PATCH_JMP_ENABLES_LO   0x0473
 
#define VL53L1_PATCH_DATA_ENABLES   0x0474
 
#define VL53L1_PATCH_DATA_ENABLES_HI   0x0474
 
#define VL53L1_PATCH_DATA_ENABLES_LO   0x0475
 
#define VL53L1_PATCH_OFFSET_0   0x0476
 
#define VL53L1_PATCH_OFFSET_0_HI   0x0476
 
#define VL53L1_PATCH_OFFSET_0_LO   0x0477
 
#define VL53L1_PATCH_OFFSET_1   0x0478
 
#define VL53L1_PATCH_OFFSET_1_HI   0x0478
 
#define VL53L1_PATCH_OFFSET_1_LO   0x0479
 
#define VL53L1_PATCH_OFFSET_2   0x047A
 
#define VL53L1_PATCH_OFFSET_2_HI   0x047A
 
#define VL53L1_PATCH_OFFSET_2_LO   0x047B
 
#define VL53L1_PATCH_OFFSET_3   0x047C
 
#define VL53L1_PATCH_OFFSET_3_HI   0x047C
 
#define VL53L1_PATCH_OFFSET_3_LO   0x047D
 
#define VL53L1_PATCH_OFFSET_4   0x047E
 
#define VL53L1_PATCH_OFFSET_4_HI   0x047E
 
#define VL53L1_PATCH_OFFSET_4_LO   0x047F
 
#define VL53L1_PATCH_OFFSET_5   0x0480
 
#define VL53L1_PATCH_OFFSET_5_HI   0x0480
 
#define VL53L1_PATCH_OFFSET_5_LO   0x0481
 
#define VL53L1_PATCH_OFFSET_6   0x0482
 
#define VL53L1_PATCH_OFFSET_6_HI   0x0482
 
#define VL53L1_PATCH_OFFSET_6_LO   0x0483
 
#define VL53L1_PATCH_OFFSET_7   0x0484
 
#define VL53L1_PATCH_OFFSET_7_HI   0x0484
 
#define VL53L1_PATCH_OFFSET_7_LO   0x0485
 
#define VL53L1_PATCH_OFFSET_8   0x0486
 
#define VL53L1_PATCH_OFFSET_8_HI   0x0486
 
#define VL53L1_PATCH_OFFSET_8_LO   0x0487
 
#define VL53L1_PATCH_OFFSET_9   0x0488
 
#define VL53L1_PATCH_OFFSET_9_HI   0x0488
 
#define VL53L1_PATCH_OFFSET_9_LO   0x0489
 
#define VL53L1_PATCH_OFFSET_10   0x048A
 
#define VL53L1_PATCH_OFFSET_10_HI   0x048A
 
#define VL53L1_PATCH_OFFSET_10_LO   0x048B
 
#define VL53L1_PATCH_OFFSET_11   0x048C
 
#define VL53L1_PATCH_OFFSET_11_HI   0x048C
 
#define VL53L1_PATCH_OFFSET_11_LO   0x048D
 
#define VL53L1_PATCH_OFFSET_12   0x048E
 
#define VL53L1_PATCH_OFFSET_12_HI   0x048E
 
#define VL53L1_PATCH_OFFSET_12_LO   0x048F
 
#define VL53L1_PATCH_OFFSET_13   0x0490
 
#define VL53L1_PATCH_OFFSET_13_HI   0x0490
 
#define VL53L1_PATCH_OFFSET_13_LO   0x0491
 
#define VL53L1_PATCH_OFFSET_14   0x0492
 
#define VL53L1_PATCH_OFFSET_14_HI   0x0492
 
#define VL53L1_PATCH_OFFSET_14_LO   0x0493
 
#define VL53L1_PATCH_OFFSET_15   0x0494
 
#define VL53L1_PATCH_OFFSET_15_HI   0x0494
 
#define VL53L1_PATCH_OFFSET_15_LO   0x0495
 
#define VL53L1_PATCH_ADDRESS_0   0x0496
 
#define VL53L1_PATCH_ADDRESS_0_HI   0x0496
 
#define VL53L1_PATCH_ADDRESS_0_LO   0x0497
 
#define VL53L1_PATCH_ADDRESS_1   0x0498
 
#define VL53L1_PATCH_ADDRESS_1_HI   0x0498
 
#define VL53L1_PATCH_ADDRESS_1_LO   0x0499
 
#define VL53L1_PATCH_ADDRESS_2   0x049A
 
#define VL53L1_PATCH_ADDRESS_2_HI   0x049A
 
#define VL53L1_PATCH_ADDRESS_2_LO   0x049B
 
#define VL53L1_PATCH_ADDRESS_3   0x049C
 
#define VL53L1_PATCH_ADDRESS_3_HI   0x049C
 
#define VL53L1_PATCH_ADDRESS_3_LO   0x049D
 
#define VL53L1_PATCH_ADDRESS_4   0x049E
 
#define VL53L1_PATCH_ADDRESS_4_HI   0x049E
 
#define VL53L1_PATCH_ADDRESS_4_LO   0x049F
 
#define VL53L1_PATCH_ADDRESS_5   0x04A0
 
#define VL53L1_PATCH_ADDRESS_5_HI   0x04A0
 
#define VL53L1_PATCH_ADDRESS_5_LO   0x04A1
 
#define VL53L1_PATCH_ADDRESS_6   0x04A2
 
#define VL53L1_PATCH_ADDRESS_6_HI   0x04A2
 
#define VL53L1_PATCH_ADDRESS_6_LO   0x04A3
 
#define VL53L1_PATCH_ADDRESS_7   0x04A4
 
#define VL53L1_PATCH_ADDRESS_7_HI   0x04A4
 
#define VL53L1_PATCH_ADDRESS_7_LO   0x04A5
 
#define VL53L1_PATCH_ADDRESS_8   0x04A6
 
#define VL53L1_PATCH_ADDRESS_8_HI   0x04A6
 
#define VL53L1_PATCH_ADDRESS_8_LO   0x04A7
 
#define VL53L1_PATCH_ADDRESS_9   0x04A8
 
#define VL53L1_PATCH_ADDRESS_9_HI   0x04A8
 
#define VL53L1_PATCH_ADDRESS_9_LO   0x04A9
 
#define VL53L1_PATCH_ADDRESS_10   0x04AA
 
#define VL53L1_PATCH_ADDRESS_10_HI   0x04AA
 
#define VL53L1_PATCH_ADDRESS_10_LO   0x04AB
 
#define VL53L1_PATCH_ADDRESS_11   0x04AC
 
#define VL53L1_PATCH_ADDRESS_11_HI   0x04AC
 
#define VL53L1_PATCH_ADDRESS_11_LO   0x04AD
 
#define VL53L1_PATCH_ADDRESS_12   0x04AE
 
#define VL53L1_PATCH_ADDRESS_12_HI   0x04AE
 
#define VL53L1_PATCH_ADDRESS_12_LO   0x04AF
 
#define VL53L1_PATCH_ADDRESS_13   0x04B0
 
#define VL53L1_PATCH_ADDRESS_13_HI   0x04B0
 
#define VL53L1_PATCH_ADDRESS_13_LO   0x04B1
 
#define VL53L1_PATCH_ADDRESS_14   0x04B2
 
#define VL53L1_PATCH_ADDRESS_14_HI   0x04B2
 
#define VL53L1_PATCH_ADDRESS_14_LO   0x04B3
 
#define VL53L1_PATCH_ADDRESS_15   0x04B4
 
#define VL53L1_PATCH_ADDRESS_15_HI   0x04B4
 
#define VL53L1_PATCH_ADDRESS_15_LO   0x04B5
 
#define VL53L1_SPI_ASYNC_MUX_CTRL   0x04C0
 
#define VL53L1_CLK_CONFIG   0x04C4
 
#define VL53L1_GPIO_LV_MUX_CTRL   0x04CC
 
#define VL53L1_GPIO_LV_PAD_CTRL   0x04CD
 
#define VL53L1_PAD_I2C_LV_CONFIG   0x04D0
 
#define VL53L1_PAD_STARTUP_MODE_VALUE_RO_GO1   0x04D4
 
#define VL53L1_HOST_IF_STATUS_GO1   0x04D5
 
#define VL53L1_MCU_CLK_GATING_CTRL   0x04D8
 
#define VL53L1_TEST_BIST_ROM_CTRL   0x04E0
 
#define VL53L1_TEST_BIST_ROM_RESULT   0x04E1
 
#define VL53L1_TEST_BIST_ROM_MCU_SIG   0x04E2
 
#define VL53L1_TEST_BIST_ROM_MCU_SIG_HI   0x04E2
 
#define VL53L1_TEST_BIST_ROM_MCU_SIG_LO   0x04E3
 
#define VL53L1_TEST_BIST_RAM_CTRL   0x04E4
 
#define VL53L1_TEST_BIST_RAM_RESULT   0x04E5
 
#define VL53L1_TEST_TMC   0x04E8
 
#define VL53L1_TEST_PLL_BIST_MIN_THRESHOLD   0x04F0
 
#define VL53L1_TEST_PLL_BIST_MIN_THRESHOLD_HI   0x04F0
 
#define VL53L1_TEST_PLL_BIST_MIN_THRESHOLD_LO   0x04F1
 
#define VL53L1_TEST_PLL_BIST_MAX_THRESHOLD   0x04F2
 
#define VL53L1_TEST_PLL_BIST_MAX_THRESHOLD_HI   0x04F2
 
#define VL53L1_TEST_PLL_BIST_MAX_THRESHOLD_LO   0x04F3
 
#define VL53L1_TEST_PLL_BIST_COUNT_OUT   0x04F4
 
#define VL53L1_TEST_PLL_BIST_COUNT_OUT_HI   0x04F4
 
#define VL53L1_TEST_PLL_BIST_COUNT_OUT_LO   0x04F5
 
#define VL53L1_TEST_PLL_BIST_GONOGO   0x04F6
 
#define VL53L1_TEST_PLL_BIST_CTRL   0x04F7
 
#define VL53L1_RANGING_CORE_DEVICE_ID   0x0680
 
#define VL53L1_RANGING_CORE_REVISION_ID   0x0681
 
#define VL53L1_RANGING_CORE_CLK_CTRL1   0x0683
 
#define VL53L1_RANGING_CORE_CLK_CTRL2   0x0684
 
#define VL53L1_RANGING_CORE_WOI_1   0x0685
 
#define VL53L1_RANGING_CORE_WOI_REF_1   0x0686
 
#define VL53L1_RANGING_CORE_START_RANGING   0x0687
 
#define VL53L1_RANGING_CORE_LOW_LIMIT_1   0x0690
 
#define VL53L1_RANGING_CORE_HIGH_LIMIT_1   0x0691
 
#define VL53L1_RANGING_CORE_LOW_LIMIT_REF_1   0x0692
 
#define VL53L1_RANGING_CORE_HIGH_LIMIT_REF_1   0x0693
 
#define VL53L1_RANGING_CORE_QUANTIFIER_1_MSB   0x0694
 
#define VL53L1_RANGING_CORE_QUANTIFIER_1_LSB   0x0695
 
#define VL53L1_RANGING_CORE_QUANTIFIER_REF_1_MSB   0x0696
 
#define VL53L1_RANGING_CORE_QUANTIFIER_REF_1_LSB   0x0697
 
#define VL53L1_RANGING_CORE_AMBIENT_OFFSET_1_MSB   0x0698
 
#define VL53L1_RANGING_CORE_AMBIENT_OFFSET_1_LSB   0x0699
 
#define VL53L1_RANGING_CORE_AMBIENT_OFFSET_REF_1_MSB   0x069A
 
#define VL53L1_RANGING_CORE_AMBIENT_OFFSET_REF_1_LSB   0x069B
 
#define VL53L1_RANGING_CORE_FILTER_STRENGTH_1   0x069C
 
#define VL53L1_RANGING_CORE_FILTER_STRENGTH_REF_1   0x069D
 
#define VL53L1_RANGING_CORE_SIGNAL_EVENT_LIMIT_1_MSB   0x069E
 
#define VL53L1_RANGING_CORE_SIGNAL_EVENT_LIMIT_1_LSB   0x069F
 
#define VL53L1_RANGING_CORE_SIGNAL_EVENT_LIMIT_REF_1_MSB   0x06A0
 
#define VL53L1_RANGING_CORE_SIGNAL_EVENT_LIMIT_REF_1_LSB   0x06A1
 
#define VL53L1_RANGING_CORE_TIMEOUT_OVERALL_PERIODS_MSB   0x06A4
 
#define VL53L1_RANGING_CORE_TIMEOUT_OVERALL_PERIODS_LSB   0x06A5
 
#define VL53L1_RANGING_CORE_INVERT_HW   0x06A6
 
#define VL53L1_RANGING_CORE_FORCE_HW   0x06A7
 
#define VL53L1_RANGING_CORE_STATIC_HW_VALUE   0x06A8
 
#define VL53L1_RANGING_CORE_FORCE_CONTINUOUS_AMBIENT   0x06A9
 
#define VL53L1_RANGING_CORE_TEST_PHASE_SELECT_TO_FILTER   0x06AA
 
#define VL53L1_RANGING_CORE_TEST_PHASE_SELECT_TO_TIMING_GEN   0x06AB
 
#define VL53L1_RANGING_CORE_INITIAL_PHASE_VALUE_1   0x06AC
 
#define VL53L1_RANGING_CORE_INITIAL_PHASE_VALUE_REF_1   0x06AD
 
#define VL53L1_RANGING_CORE_FORCE_UP_IN   0x06AE
 
#define VL53L1_RANGING_CORE_FORCE_DN_IN   0x06AF
 
#define VL53L1_RANGING_CORE_STATIC_UP_VALUE_1   0x06B0
 
#define VL53L1_RANGING_CORE_STATIC_UP_VALUE_REF_1   0x06B1
 
#define VL53L1_RANGING_CORE_STATIC_DN_VALUE_1   0x06B2
 
#define VL53L1_RANGING_CORE_STATIC_DN_VALUE_REF_1   0x06B3
 
#define VL53L1_RANGING_CORE_MONITOR_UP_DN   0x06B4
 
#define VL53L1_RANGING_CORE_INVERT_UP_DN   0x06B5
 
#define VL53L1_RANGING_CORE_CPUMP_1   0x06B6
 
#define VL53L1_RANGING_CORE_CPUMP_2   0x06B7
 
#define VL53L1_RANGING_CORE_CPUMP_3   0x06B8
 
#define VL53L1_RANGING_CORE_OSC_1   0x06B9
 
#define VL53L1_RANGING_CORE_PLL_1   0x06BB
 
#define VL53L1_RANGING_CORE_PLL_2   0x06BC
 
#define VL53L1_RANGING_CORE_REFERENCE_1   0x06BD
 
#define VL53L1_RANGING_CORE_REFERENCE_3   0x06BF
 
#define VL53L1_RANGING_CORE_REFERENCE_4   0x06C0
 
#define VL53L1_RANGING_CORE_REFERENCE_5   0x06C1
 
#define VL53L1_RANGING_CORE_REGAVDD1V2   0x06C3
 
#define VL53L1_RANGING_CORE_CALIB_1   0x06C4
 
#define VL53L1_RANGING_CORE_CALIB_2   0x06C5
 
#define VL53L1_RANGING_CORE_CALIB_3   0x06C6
 
#define VL53L1_RANGING_CORE_TST_MUX_SEL1   0x06C9
 
#define VL53L1_RANGING_CORE_TST_MUX_SEL2   0x06CA
 
#define VL53L1_RANGING_CORE_TST_MUX   0x06CB
 
#define VL53L1_RANGING_CORE_GPIO_OUT_TESTMUX   0x06CC
 
#define VL53L1_RANGING_CORE_CUSTOM_FE   0x06CD
 
#define VL53L1_RANGING_CORE_CUSTOM_FE_2   0x06CE
 
#define VL53L1_RANGING_CORE_SPAD_READOUT   0x06CF
 
#define VL53L1_RANGING_CORE_SPAD_READOUT_1   0x06D0
 
#define VL53L1_RANGING_CORE_SPAD_READOUT_2   0x06D1
 
#define VL53L1_RANGING_CORE_SPAD_PS   0x06D2
 
#define VL53L1_RANGING_CORE_LASER_SAFETY_2   0x06D4
 
#define VL53L1_RANGING_CORE_NVM_CTRL_MODE   0x0780
 
#define VL53L1_RANGING_CORE_NVM_CTRL_PDN   0x0781
 
#define VL53L1_RANGING_CORE_NVM_CTRL_PROGN   0x0782
 
#define VL53L1_RANGING_CORE_NVM_CTRL_READN   0x0783
 
#define VL53L1_RANGING_CORE_NVM_CTRL_PULSE_WIDTH_MSB   0x0784
 
#define VL53L1_RANGING_CORE_NVM_CTRL_PULSE_WIDTH_LSB   0x0785
 
#define VL53L1_RANGING_CORE_NVM_CTRL_HV_RISE_MSB   0x0786
 
#define VL53L1_RANGING_CORE_NVM_CTRL_HV_RISE_LSB   0x0787
 
#define VL53L1_RANGING_CORE_NVM_CTRL_HV_FALL_MSB   0x0788
 
#define VL53L1_RANGING_CORE_NVM_CTRL_HV_FALL_LSB   0x0789
 
#define VL53L1_RANGING_CORE_NVM_CTRL_TST   0x078A
 
#define VL53L1_RANGING_CORE_NVM_CTRL_TESTREAD   0x078B
 
#define VL53L1_RANGING_CORE_NVM_CTRL_DATAIN_MMM   0x078C
 
#define VL53L1_RANGING_CORE_NVM_CTRL_DATAIN_LMM   0x078D
 
#define VL53L1_RANGING_CORE_NVM_CTRL_DATAIN_LLM   0x078E
 
#define VL53L1_RANGING_CORE_NVM_CTRL_DATAIN_LLL   0x078F
 
#define VL53L1_RANGING_CORE_NVM_CTRL_DATAOUT_MMM   0x0790
 
#define VL53L1_RANGING_CORE_NVM_CTRL_DATAOUT_LMM   0x0791
 
#define VL53L1_RANGING_CORE_NVM_CTRL_DATAOUT_LLM   0x0792
 
#define VL53L1_RANGING_CORE_NVM_CTRL_DATAOUT_LLL   0x0793
 
#define VL53L1_RANGING_CORE_NVM_CTRL_ADDR   0x0794
 
#define VL53L1_RANGING_CORE_NVM_CTRL_DATAOUT_ECC   0x0795
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_0   0x0796
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_1   0x0797
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_2   0x0798
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_3   0x0799
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_4   0x079A
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_5   0x079B
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_6   0x079C
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_7   0x079D
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_8   0x079E
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_9   0x079F
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_10   0x07A0
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_11   0x07A1
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_12   0x07A2
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_13   0x07A3
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_14   0x07A4
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_15   0x07A5
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_16   0x07A6
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_17   0x07A7
 
#define VL53L1_RANGING_CORE_SPAD_SHIFT_EN   0x07BA
 
#define VL53L1_RANGING_CORE_SPAD_DISABLE_CTRL   0x07BB
 
#define VL53L1_RANGING_CORE_SPAD_EN_SHIFT_OUT_DEBUG   0x07BC
 
#define VL53L1_RANGING_CORE_SPI_MODE   0x07BD
 
#define VL53L1_RANGING_CORE_GPIO_DIR   0x07BE
 
#define VL53L1_RANGING_CORE_VCSEL_PERIOD   0x0880
 
#define VL53L1_RANGING_CORE_VCSEL_START   0x0881
 
#define VL53L1_RANGING_CORE_VCSEL_STOP   0x0882
 
#define VL53L1_RANGING_CORE_VCSEL_1   0x0885
 
#define VL53L1_RANGING_CORE_VCSEL_STATUS   0x088D
 
#define VL53L1_RANGING_CORE_STATUS   0x0980
 
#define VL53L1_RANGING_CORE_LASER_CONTINUITY_STATE   0x0981
 
#define VL53L1_RANGING_CORE_RANGE_1_MMM   0x0982
 
#define VL53L1_RANGING_CORE_RANGE_1_LMM   0x0983
 
#define VL53L1_RANGING_CORE_RANGE_1_LLM   0x0984
 
#define VL53L1_RANGING_CORE_RANGE_1_LLL   0x0985
 
#define VL53L1_RANGING_CORE_RANGE_REF_1_MMM   0x0986
 
#define VL53L1_RANGING_CORE_RANGE_REF_1_LMM   0x0987
 
#define VL53L1_RANGING_CORE_RANGE_REF_1_LLM   0x0988
 
#define VL53L1_RANGING_CORE_RANGE_REF_1_LLL   0x0989
 
#define VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_1_MMM   0x098A
 
#define VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_1_LMM   0x098B
 
#define VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_1_LLM   0x098C
 
#define VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_1_LLL   0x098D
 
#define VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_1_MMM   0x098E
 
#define VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_1_LMM   0x098F
 
#define VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_1_LLM   0x0990
 
#define VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_1_LLL   0x0991
 
#define VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_1_MMM   0x0992
 
#define VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_1_LMM   0x0993
 
#define VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_1_LLM   0x0994
 
#define VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_1_LLL   0x0995
 
#define VL53L1_RANGING_CORE_TOTAL_PERIODS_ELAPSED_1_MM   0x0996
 
#define VL53L1_RANGING_CORE_TOTAL_PERIODS_ELAPSED_1_LM   0x0997
 
#define VL53L1_RANGING_CORE_TOTAL_PERIODS_ELAPSED_1_LL   0x0998
 
#define VL53L1_RANGING_CORE_AMBIENT_MISMATCH_MM   0x0999
 
#define VL53L1_RANGING_CORE_AMBIENT_MISMATCH_LM   0x099A
 
#define VL53L1_RANGING_CORE_AMBIENT_MISMATCH_LL   0x099B
 
#define VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_REF_1_MMM   0x099C
 
#define VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_REF_1_LMM   0x099D
 
#define VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_REF_1_LLM   0x099E
 
#define VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_REF_1_LLL   0x099F
 
#define VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_REF_1_MMM   0x09A0
 
#define VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_REF_1_LMM   0x09A1
 
#define VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_REF_1_LLM   0x09A2
 
#define VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_REF_1_LLL   0x09A3
 
#define VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_REF_1_MMM   0x09A4
 
#define VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_REF_1_LMM   0x09A5
 
#define VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_REF_1_LLM   0x09A6
 
#define VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_REF_1_LLL   0x09A7
 
#define VL53L1_RANGING_CORE_TOTAL_PERIODS_ELAPSED_REF_1_MM   0x09A8
 
#define VL53L1_RANGING_CORE_TOTAL_PERIODS_ELAPSED_REF_1_LM   0x09A9
 
#define VL53L1_RANGING_CORE_TOTAL_PERIODS_ELAPSED_REF_1_LL   0x09AA
 
#define VL53L1_RANGING_CORE_AMBIENT_MISMATCH_REF_MM   0x09AB
 
#define VL53L1_RANGING_CORE_AMBIENT_MISMATCH_REF_LM   0x09AC
 
#define VL53L1_RANGING_CORE_AMBIENT_MISMATCH_REF_LL   0x09AD
 
#define VL53L1_RANGING_CORE_GPIO_CONFIG_A0   0x0A00
 
#define VL53L1_RANGING_CORE_RESET_CONTROL_A0   0x0A01
 
#define VL53L1_RANGING_CORE_INTR_MANAGER_A0   0x0A02
 
#define VL53L1_RANGING_CORE_POWER_FSM_TIME_OSC_A0   0x0A06
 
#define VL53L1_RANGING_CORE_VCSEL_ATEST_A0   0x0A07
 
#define VL53L1_RANGING_CORE_VCSEL_PERIOD_CLIPPED_A0   0x0A08
 
#define VL53L1_RANGING_CORE_VCSEL_STOP_CLIPPED_A0   0x0A09
 
#define VL53L1_RANGING_CORE_CALIB_2_A0   0x0A0A
 
#define VL53L1_RANGING_CORE_STOP_CONDITION_A0   0x0A0B
 
#define VL53L1_RANGING_CORE_STATUS_RESET_A0   0x0A0C
 
#define VL53L1_RANGING_CORE_READOUT_CFG_A0   0x0A0D
 
#define VL53L1_RANGING_CORE_WINDOW_SETTING_A0   0x0A0E
 
#define VL53L1_RANGING_CORE_VCSEL_DELAY_A0   0x0A1A
 
#define VL53L1_RANGING_CORE_REFERENCE_2_A0   0x0A1B
 
#define VL53L1_RANGING_CORE_REGAVDD1V2_A0   0x0A1D
 
#define VL53L1_RANGING_CORE_TST_MUX_A0   0x0A1F
 
#define VL53L1_RANGING_CORE_CUSTOM_FE_2_A0   0x0A20
 
#define VL53L1_RANGING_CORE_SPAD_READOUT_A0   0x0A21
 
#define VL53L1_RANGING_CORE_CPUMP_1_A0   0x0A22
 
#define VL53L1_RANGING_CORE_SPARE_REGISTER_A0   0x0A23
 
#define VL53L1_RANGING_CORE_VCSEL_CONT_STAGE5_BYPASS_A0   0x0A24
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_18   0x0A25
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_19   0x0A26
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_20   0x0A27
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_21   0x0A28
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_22   0x0A29
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_23   0x0A2A
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_24   0x0A2B
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_25   0x0A2C
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_26   0x0A2D
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_27   0x0A2E
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_28   0x0A2F
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_29   0x0A30
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_30   0x0A31
 
#define VL53L1_RANGING_CORE_RET_SPAD_EN_31   0x0A32
 
#define VL53L1_RANGING_CORE_REF_SPAD_EN_0_EWOK   0x0A33
 
#define VL53L1_RANGING_CORE_REF_SPAD_EN_1_EWOK   0x0A34
 
#define VL53L1_RANGING_CORE_REF_SPAD_EN_2_EWOK   0x0A35
 
#define VL53L1_RANGING_CORE_REF_SPAD_EN_3_EWOK   0x0A36
 
#define VL53L1_RANGING_CORE_REF_SPAD_EN_4_EWOK   0x0A37
 
#define VL53L1_RANGING_CORE_REF_SPAD_EN_5_EWOK   0x0A38
 
#define VL53L1_RANGING_CORE_REF_EN_START_SELECT   0x0A39
 
#define VL53L1_RANGING_CORE_REGDVDD1V2_ATEST_EWOK   0x0A41
 
#define VL53L1_SOFT_RESET_GO1   0x0B00
 
#define VL53L1_PRIVATE_PATCH_BASE_ADDR_RSLV   0x0E00
 
#define VL53L1_PREV_SHADOW_RESULT_INTERRUPT_STATUS   0x0ED0
 
#define VL53L1_PREV_SHADOW_RESULT_RANGE_STATUS   0x0ED1
 
#define VL53L1_PREV_SHADOW_RESULT_REPORT_STATUS   0x0ED2
 
#define VL53L1_PREV_SHADOW_RESULT_STREAM_COUNT   0x0ED3
 
#define VL53L1_PREV_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0   0x0ED4
 
#define VL53L1_PREV_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI   0x0ED4
 
#define VL53L1_PREV_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO   0x0ED5
 
#define VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0   0x0ED6
 
#define VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI   0x0ED6
 
#define VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO   0x0ED7
 
#define VL53L1_PREV_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0   0x0ED8
 
#define VL53L1_PREV_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0_HI   0x0ED8
 
#define VL53L1_PREV_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0_LO   0x0ED9
 
#define VL53L1_PREV_SHADOW_RESULT_SIGMA_SD0   0x0EDA
 
#define VL53L1_PREV_SHADOW_RESULT_SIGMA_SD0_HI   0x0EDA
 
#define VL53L1_PREV_SHADOW_RESULT_SIGMA_SD0_LO   0x0EDB
 
#define VL53L1_PREV_SHADOW_RESULT_PHASE_SD0   0x0EDC
 
#define VL53L1_PREV_SHADOW_RESULT_PHASE_SD0_HI   0x0EDC
 
#define VL53L1_PREV_SHADOW_RESULT_PHASE_SD0_LO   0x0EDD
 
#define VL53L1_PREV_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0   0x0EDE
 
#define VL53L1_PREV_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI   0x0EDE
 
#define VL53L1_PREV_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO   0x0EDF
 
#define VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0   0x0EE0
 
#define VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI   0x0EE0
 
#define VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO   0x0EE1
 
#define VL53L1_PREV_SHADOW_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0   0x0EE2
 
#define VL53L1_PREV_SHADOW_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI   0x0EE2
 
#define VL53L1_PREV_SHADOW_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO   0x0EE3
 
#define VL53L1_PREV_SHADOW_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0   0x0EE4
 
#define VL53L1_PREV_SHADOW_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI   0x0EE4
 
#define VL53L1_PREV_SHADOW_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO   0x0EE5
 
#define VL53L1_PREV_SHADOW_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0   0x0EE6
 
#define VL53L1_PREV_SHADOW_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI   0x0EE6
 
#define VL53L1_PREV_SHADOW_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO   0x0EE7
 
#define VL53L1_PREV_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1   0x0EE8
 
#define VL53L1_PREV_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI   0x0EE8
 
#define VL53L1_PREV_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO   0x0EE9
 
#define VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1   0x0EEA
 
#define VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI   0x0EEA
 
#define VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO   0x0EEB
 
#define VL53L1_PREV_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1   0x0EEC
 
#define VL53L1_PREV_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1_HI   0x0EEC
 
#define VL53L1_PREV_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1_LO   0x0EED
 
#define VL53L1_PREV_SHADOW_RESULT_SIGMA_SD1   0x0EEE
 
#define VL53L1_PREV_SHADOW_RESULT_SIGMA_SD1_HI   0x0EEE
 
#define VL53L1_PREV_SHADOW_RESULT_SIGMA_SD1_LO   0x0EEF
 
#define VL53L1_PREV_SHADOW_RESULT_PHASE_SD1   0x0EF0
 
#define VL53L1_PREV_SHADOW_RESULT_PHASE_SD1_HI   0x0EF0
 
#define VL53L1_PREV_SHADOW_RESULT_PHASE_SD1_LO   0x0EF1
 
#define VL53L1_PREV_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1   0x0EF2
 
#define VL53L1_PREV_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI   0x0EF2
 
#define VL53L1_PREV_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO   0x0EF3
 
#define VL53L1_PREV_SHADOW_RESULT_SPARE_0_SD1   0x0EF4
 
#define VL53L1_PREV_SHADOW_RESULT_SPARE_0_SD1_HI   0x0EF4
 
#define VL53L1_PREV_SHADOW_RESULT_SPARE_0_SD1_LO   0x0EF5
 
#define VL53L1_PREV_SHADOW_RESULT_SPARE_1_SD1   0x0EF6
 
#define VL53L1_PREV_SHADOW_RESULT_SPARE_1_SD1_HI   0x0EF6
 
#define VL53L1_PREV_SHADOW_RESULT_SPARE_1_SD1_LO   0x0EF7
 
#define VL53L1_PREV_SHADOW_RESULT_SPARE_2_SD1   0x0EF8
 
#define VL53L1_PREV_SHADOW_RESULT_SPARE_2_SD1_HI   0x0EF8
 
#define VL53L1_PREV_SHADOW_RESULT_SPARE_2_SD1_LO   0x0EF9
 
#define VL53L1_PREV_SHADOW_RESULT_SPARE_3_SD1   0x0EFA
 
#define VL53L1_PREV_SHADOW_RESULT_SPARE_3_SD1_HI   0x0EFA
 
#define VL53L1_PREV_SHADOW_RESULT_SPARE_3_SD1_LO   0x0EFB
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0   0x0EFC
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_3   0x0EFC
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_2   0x0EFD
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_1   0x0EFE
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_0   0x0EFF
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0   0x0F00
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_3   0x0F00
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_2   0x0F01
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_1   0x0F02
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_0   0x0F03
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0   0x0F04
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_3   0x0F04
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_2   0x0F05
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_1   0x0F06
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_0   0x0F07
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0   0x0F08
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_3   0x0F08
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_2   0x0F09
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_1   0x0F0A
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_0   0x0F0B
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1   0x0F0C
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_3   0x0F0C
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_2   0x0F0D
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_1   0x0F0E
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_0   0x0F0F
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1   0x0F10
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_3   0x0F10
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_2   0x0F11
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_1   0x0F12
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_0   0x0F13
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1   0x0F14
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_3   0x0F14
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_2   0x0F15
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_1   0x0F16
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_0   0x0F17
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1   0x0F18
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_3   0x0F18
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_2   0x0F19
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_1   0x0F1A
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_0   0x0F1B
 
#define VL53L1_PREV_SHADOW_RESULT_CORE_SPARE_0   0x0F1C
 
#define VL53L1_RESULT_DEBUG_STATUS   0x0F20
 
#define VL53L1_RESULT_DEBUG_STAGE   0x0F21
 
#define VL53L1_GPH_SYSTEM_THRESH_RATE_HIGH   0x0F24
 
#define VL53L1_GPH_SYSTEM_THRESH_RATE_HIGH_HI   0x0F24
 
#define VL53L1_GPH_SYSTEM_THRESH_RATE_HIGH_LO   0x0F25
 
#define VL53L1_GPH_SYSTEM_THRESH_RATE_LOW   0x0F26
 
#define VL53L1_GPH_SYSTEM_THRESH_RATE_LOW_HI   0x0F26
 
#define VL53L1_GPH_SYSTEM_THRESH_RATE_LOW_LO   0x0F27
 
#define VL53L1_GPH_SYSTEM_INTERRUPT_CONFIG_GPIO   0x0F28
 
#define VL53L1_GPH_DSS_CONFIG_ROI_MODE_CONTROL   0x0F2F
 
#define VL53L1_GPH_DSS_CONFIG_MANUAL_EFFECTIVE_SPADS_SELECT   0x0F30
 
#define VL53L1_GPH_DSS_CONFIG_MANUAL_EFFECTIVE_SPADS_SELECT_HI   0x0F30
 
#define VL53L1_GPH_DSS_CONFIG_MANUAL_EFFECTIVE_SPADS_SELECT_LO   0x0F31
 
#define VL53L1_GPH_DSS_CONFIG_MANUAL_BLOCK_SELECT   0x0F32
 
#define VL53L1_GPH_DSS_CONFIG_MAX_SPADS_LIMIT   0x0F33
 
#define VL53L1_GPH_DSS_CONFIG_MIN_SPADS_LIMIT   0x0F34
 
#define VL53L1_GPH_MM_CONFIG_TIMEOUT_MACROP_A_HI   0x0F36
 
#define VL53L1_GPH_MM_CONFIG_TIMEOUT_MACROP_A_LO   0x0F37
 
#define VL53L1_GPH_MM_CONFIG_TIMEOUT_MACROP_B_HI   0x0F38
 
#define VL53L1_GPH_MM_CONFIG_TIMEOUT_MACROP_B_LO   0x0F39
 
#define VL53L1_GPH_RANGE_CONFIG_TIMEOUT_MACROP_A_HI   0x0F3A
 
#define VL53L1_GPH_RANGE_CONFIG_TIMEOUT_MACROP_A_LO   0x0F3B
 
#define VL53L1_GPH_RANGE_CONFIG_VCSEL_PERIOD_A   0x0F3C
 
#define VL53L1_GPH_RANGE_CONFIG_VCSEL_PERIOD_B   0x0F3D
 
#define VL53L1_GPH_RANGE_CONFIG_TIMEOUT_MACROP_B_HI   0x0F3E
 
#define VL53L1_GPH_RANGE_CONFIG_TIMEOUT_MACROP_B_LO   0x0F3F
 
#define VL53L1_GPH_RANGE_CONFIG_SIGMA_THRESH   0x0F40
 
#define VL53L1_GPH_RANGE_CONFIG_SIGMA_THRESH_HI   0x0F40
 
#define VL53L1_GPH_RANGE_CONFIG_SIGMA_THRESH_LO   0x0F41
 
#define VL53L1_GPH_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT_MCPS   0x0F42
 
#define VL53L1_GPH_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI   0x0F42
 
#define VL53L1_GPH_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO   0x0F43
 
#define VL53L1_GPH_RANGE_CONFIG_VALID_PHASE_LOW   0x0F44
 
#define VL53L1_GPH_RANGE_CONFIG_VALID_PHASE_HIGH   0x0F45
 
#define VL53L1_FIRMWARE_INTERNAL_STREAM_COUNT_DIV   0x0F46
 
#define VL53L1_FIRMWARE_INTERNAL_STREAM_COUNTER_VAL   0x0F47
 
#define VL53L1_DSS_CALC_ROI_CTRL   0x0F54
 
#define VL53L1_DSS_CALC_SPARE_1   0x0F55
 
#define VL53L1_DSS_CALC_SPARE_2   0x0F56
 
#define VL53L1_DSS_CALC_SPARE_3   0x0F57
 
#define VL53L1_DSS_CALC_SPARE_4   0x0F58
 
#define VL53L1_DSS_CALC_SPARE_5   0x0F59
 
#define VL53L1_DSS_CALC_SPARE_6   0x0F5A
 
#define VL53L1_DSS_CALC_SPARE_7   0x0F5B
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_0   0x0F5C
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_1   0x0F5D
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_2   0x0F5E
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_3   0x0F5F
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_4   0x0F60
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_5   0x0F61
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_6   0x0F62
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_7   0x0F63
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_8   0x0F64
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_9   0x0F65
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_10   0x0F66
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_11   0x0F67
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_12   0x0F68
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_13   0x0F69
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_14   0x0F6A
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_15   0x0F6B
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_16   0x0F6C
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_17   0x0F6D
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_18   0x0F6E
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_19   0x0F6F
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_20   0x0F70
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_21   0x0F71
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_22   0x0F72
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_23   0x0F73
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_24   0x0F74
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_25   0x0F75
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_26   0x0F76
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_27   0x0F77
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_28   0x0F78
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_29   0x0F79
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_30   0x0F7A
 
#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_31   0x0F7B
 
#define VL53L1_DSS_CALC_USER_ROI_0   0x0F7C
 
#define VL53L1_DSS_CALC_USER_ROI_1   0x0F7D
 
#define VL53L1_DSS_CALC_MODE_ROI_0   0x0F7E
 
#define VL53L1_DSS_CALC_MODE_ROI_1   0x0F7F
 
#define VL53L1_SIGMA_ESTIMATOR_CALC_SPARE_0   0x0F80
 
#define VL53L1_VHV_RESULT_PEAK_SIGNAL_RATE_MCPS   0x0F82
 
#define VL53L1_VHV_RESULT_PEAK_SIGNAL_RATE_MCPS_HI   0x0F82
 
#define VL53L1_VHV_RESULT_PEAK_SIGNAL_RATE_MCPS_LO   0x0F83
 
#define VL53L1_VHV_RESULT_SIGNAL_TOTAL_EVENTS_REF   0x0F84
 
#define VL53L1_VHV_RESULT_SIGNAL_TOTAL_EVENTS_REF_3   0x0F84
 
#define VL53L1_VHV_RESULT_SIGNAL_TOTAL_EVENTS_REF_2   0x0F85
 
#define VL53L1_VHV_RESULT_SIGNAL_TOTAL_EVENTS_REF_1   0x0F86
 
#define VL53L1_VHV_RESULT_SIGNAL_TOTAL_EVENTS_REF_0   0x0F87
 
#define VL53L1_PHASECAL_RESULT_PHASE_OUTPUT_REF   0x0F88
 
#define VL53L1_PHASECAL_RESULT_PHASE_OUTPUT_REF_HI   0x0F88
 
#define VL53L1_PHASECAL_RESULT_PHASE_OUTPUT_REF_LO   0x0F89
 
#define VL53L1_DSS_RESULT_TOTAL_RATE_PER_SPAD   0x0F8A
 
#define VL53L1_DSS_RESULT_TOTAL_RATE_PER_SPAD_HI   0x0F8A
 
#define VL53L1_DSS_RESULT_TOTAL_RATE_PER_SPAD_LO   0x0F8B
 
#define VL53L1_DSS_RESULT_ENABLED_BLOCKS   0x0F8C
 
#define VL53L1_DSS_RESULT_NUM_REQUESTED_SPADS   0x0F8E
 
#define VL53L1_DSS_RESULT_NUM_REQUESTED_SPADS_HI   0x0F8E
 
#define VL53L1_DSS_RESULT_NUM_REQUESTED_SPADS_LO   0x0F8F
 
#define VL53L1_MM_RESULT_INNER_INTERSECTION_RATE   0x0F92
 
#define VL53L1_MM_RESULT_INNER_INTERSECTION_RATE_HI   0x0F92
 
#define VL53L1_MM_RESULT_INNER_INTERSECTION_RATE_LO   0x0F93
 
#define VL53L1_MM_RESULT_OUTER_COMPLEMENT_RATE   0x0F94
 
#define VL53L1_MM_RESULT_OUTER_COMPLEMENT_RATE_HI   0x0F94
 
#define VL53L1_MM_RESULT_OUTER_COMPLEMENT_RATE_LO   0x0F95
 
#define VL53L1_MM_RESULT_TOTAL_OFFSET   0x0F96
 
#define VL53L1_MM_RESULT_TOTAL_OFFSET_HI   0x0F96
 
#define VL53L1_MM_RESULT_TOTAL_OFFSET_LO   0x0F97
 
#define VL53L1_XTALK_CALC_XTALK_FOR_ENABLED_SPADS   0x0F98
 
#define VL53L1_XTALK_CALC_XTALK_FOR_ENABLED_SPADS_3   0x0F98
 
#define VL53L1_XTALK_CALC_XTALK_FOR_ENABLED_SPADS_2   0x0F99
 
#define VL53L1_XTALK_CALC_XTALK_FOR_ENABLED_SPADS_1   0x0F9A
 
#define VL53L1_XTALK_CALC_XTALK_FOR_ENABLED_SPADS_0   0x0F9B
 
#define VL53L1_XTALK_RESULT_AVG_XTALK_USER_ROI_KCPS   0x0F9C
 
#define VL53L1_XTALK_RESULT_AVG_XTALK_USER_ROI_KCPS_3   0x0F9C
 
#define VL53L1_XTALK_RESULT_AVG_XTALK_USER_ROI_KCPS_2   0x0F9D
 
#define VL53L1_XTALK_RESULT_AVG_XTALK_USER_ROI_KCPS_1   0x0F9E
 
#define VL53L1_XTALK_RESULT_AVG_XTALK_USER_ROI_KCPS_0   0x0F9F
 
#define VL53L1_XTALK_RESULT_AVG_XTALK_MM_INNER_ROI_KCPS   0x0FA0
 
#define VL53L1_XTALK_RESULT_AVG_XTALK_MM_INNER_ROI_KCPS_3   0x0FA0
 
#define VL53L1_XTALK_RESULT_AVG_XTALK_MM_INNER_ROI_KCPS_2   0x0FA1
 
#define VL53L1_XTALK_RESULT_AVG_XTALK_MM_INNER_ROI_KCPS_1   0x0FA2
 
#define VL53L1_XTALK_RESULT_AVG_XTALK_MM_INNER_ROI_KCPS_0   0x0FA3
 
#define VL53L1_XTALK_RESULT_AVG_XTALK_MM_OUTER_ROI_KCPS   0x0FA4
 
#define VL53L1_XTALK_RESULT_AVG_XTALK_MM_OUTER_ROI_KCPS_3   0x0FA4
 
#define VL53L1_XTALK_RESULT_AVG_XTALK_MM_OUTER_ROI_KCPS_2   0x0FA5
 
#define VL53L1_XTALK_RESULT_AVG_XTALK_MM_OUTER_ROI_KCPS_1   0x0FA6
 
#define VL53L1_XTALK_RESULT_AVG_XTALK_MM_OUTER_ROI_KCPS_0   0x0FA7
 
#define VL53L1_RANGE_RESULT_ACCUM_PHASE   0x0FA8
 
#define VL53L1_RANGE_RESULT_ACCUM_PHASE_3   0x0FA8
 
#define VL53L1_RANGE_RESULT_ACCUM_PHASE_2   0x0FA9
 
#define VL53L1_RANGE_RESULT_ACCUM_PHASE_1   0x0FAA
 
#define VL53L1_RANGE_RESULT_ACCUM_PHASE_0   0x0FAB
 
#define VL53L1_RANGE_RESULT_OFFSET_CORRECTED_RANGE   0x0FAC
 
#define VL53L1_RANGE_RESULT_OFFSET_CORRECTED_RANGE_HI   0x0FAC
 
#define VL53L1_RANGE_RESULT_OFFSET_CORRECTED_RANGE_LO   0x0FAD
 
#define VL53L1_SHADOW_PHASECAL_RESULT_VCSEL_START   0x0FAE
 
#define VL53L1_SHADOW_RESULT_INTERRUPT_STATUS   0x0FB0
 
#define VL53L1_SHADOW_RESULT_RANGE_STATUS   0x0FB1
 
#define VL53L1_SHADOW_RESULT_REPORT_STATUS   0x0FB2
 
#define VL53L1_SHADOW_RESULT_STREAM_COUNT   0x0FB3
 
#define VL53L1_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0   0x0FB4
 
#define VL53L1_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI   0x0FB4
 
#define VL53L1_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO   0x0FB5
 
#define VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0   0x0FB6
 
#define VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI   0x0FB6
 
#define VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO   0x0FB7
 
#define VL53L1_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0   0x0FB8
 
#define VL53L1_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0_HI   0x0FB8
 
#define VL53L1_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0_LO   0x0FB9
 
#define VL53L1_SHADOW_RESULT_SIGMA_SD0   0x0FBA
 
#define VL53L1_SHADOW_RESULT_SIGMA_SD0_HI   0x0FBA
 
#define VL53L1_SHADOW_RESULT_SIGMA_SD0_LO   0x0FBB
 
#define VL53L1_SHADOW_RESULT_PHASE_SD0   0x0FBC
 
#define VL53L1_SHADOW_RESULT_PHASE_SD0_HI   0x0FBC
 
#define VL53L1_SHADOW_RESULT_PHASE_SD0_LO   0x0FBD
 
#define VL53L1_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0   0x0FBE
 
#define VL53L1_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI   0x0FBE
 
#define VL53L1_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO   0x0FBF
 
#define VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0   0x0FC0
 
#define VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI   0x0FC0
 
#define VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO   0x0FC1
 
#define VL53L1_SHADOW_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0   0x0FC2
 
#define VL53L1_SHADOW_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI   0x0FC2
 
#define VL53L1_SHADOW_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO   0x0FC3
 
#define VL53L1_SHADOW_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0   0x0FC4
 
#define VL53L1_SHADOW_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI   0x0FC4
 
#define VL53L1_SHADOW_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO   0x0FC5
 
#define VL53L1_SHADOW_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0   0x0FC6
 
#define VL53L1_SHADOW_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI   0x0FC6
 
#define VL53L1_SHADOW_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO   0x0FC7
 
#define VL53L1_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1   0x0FC8
 
#define VL53L1_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI   0x0FC8
 
#define VL53L1_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO   0x0FC9
 
#define VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1   0x0FCA
 
#define VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI   0x0FCA
 
#define VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO   0x0FCB
 
#define VL53L1_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1   0x0FCC
 
#define VL53L1_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1_HI   0x0FCC
 
#define VL53L1_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1_LO   0x0FCD
 
#define VL53L1_SHADOW_RESULT_SIGMA_SD1   0x0FCE
 
#define VL53L1_SHADOW_RESULT_SIGMA_SD1_HI   0x0FCE
 
#define VL53L1_SHADOW_RESULT_SIGMA_SD1_LO   0x0FCF
 
#define VL53L1_SHADOW_RESULT_PHASE_SD1   0x0FD0
 
#define VL53L1_SHADOW_RESULT_PHASE_SD1_HI   0x0FD0
 
#define VL53L1_SHADOW_RESULT_PHASE_SD1_LO   0x0FD1
 
#define VL53L1_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1   0x0FD2
 
#define VL53L1_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI   0x0FD2
 
#define VL53L1_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO   0x0FD3
 
#define VL53L1_SHADOW_RESULT_SPARE_0_SD1   0x0FD4
 
#define VL53L1_SHADOW_RESULT_SPARE_0_SD1_HI   0x0FD4
 
#define VL53L1_SHADOW_RESULT_SPARE_0_SD1_LO   0x0FD5
 
#define VL53L1_SHADOW_RESULT_SPARE_1_SD1   0x0FD6
 
#define VL53L1_SHADOW_RESULT_SPARE_1_SD1_HI   0x0FD6
 
#define VL53L1_SHADOW_RESULT_SPARE_1_SD1_LO   0x0FD7
 
#define VL53L1_SHADOW_RESULT_SPARE_2_SD1   0x0FD8
 
#define VL53L1_SHADOW_RESULT_SPARE_2_SD1_HI   0x0FD8
 
#define VL53L1_SHADOW_RESULT_SPARE_2_SD1_LO   0x0FD9
 
#define VL53L1_SHADOW_RESULT_SPARE_3_SD1   0x0FDA
 
#define VL53L1_SHADOW_RESULT_THRESH_INFO   0x0FDB
 
#define VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0   0x0FDC
 
#define VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_3   0x0FDC
 
#define VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_2   0x0FDD
 
#define VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_1   0x0FDE
 
#define VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_0   0x0FDF
 
#define VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0   0x0FE0
 
#define VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_3   0x0FE0
 
#define VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_2   0x0FE1
 
#define VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_1   0x0FE2
 
#define VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_0   0x0FE3
 
#define VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0   0x0FE4
 
#define VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_3   0x0FE4
 
#define VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_2   0x0FE5
 
#define VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_1   0x0FE6
 
#define VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_0   0x0FE7
 
#define VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0   0x0FE8
 
#define VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_3   0x0FE8
 
#define VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_2   0x0FE9
 
#define VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_1   0x0FEA
 
#define VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_0   0x0FEB
 
#define VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1   0x0FEC
 
#define VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_3   0x0FEC
 
#define VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_2   0x0FED
 
#define VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_1   0x0FEE
 
#define VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_0   0x0FEF
 
#define VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1   0x0FF0
 
#define VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_3   0x0FF0
 
#define VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_2   0x0FF1
 
#define VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_1   0x0FF2
 
#define VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_0   0x0FF3
 
#define VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1   0x0FF4
 
#define VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_3   0x0FF4
 
#define VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_2   0x0FF5
 
#define VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_1   0x0FF6
 
#define VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_0   0x0FF7
 
#define VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1   0x0FF8
 
#define VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_3   0x0FF8
 
#define VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_2   0x0FF9
 
#define VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_1   0x0FFA
 
#define VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_0   0x0FFB
 
#define VL53L1_SHADOW_RESULT_CORE_SPARE_0   0x0FFC
 
#define VL53L1_SHADOW_PHASECAL_RESULT_REFERENCE_PHASE_HI   0x0FFE
 
#define VL53L1_SHADOW_PHASECAL_RESULT_REFERENCE_PHASE_LO   0x0FFF
 

Macro Definition Documentation

◆ VL53L1_ALGO_CONSISTENCY_CHECK_TOLERANCE

#define VL53L1_ALGO_CONSISTENCY_CHECK_TOLERANCE   0x0040

type: uint8_t
default: 0x08
info:

  • msb = 3
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'algo_config']

fields:

  • [3:0] = consistency_check_tolerance (fixed point 1.3)

◆ VL53L1_ALGO_CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS

#define VL53L1_ALGO_CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS   0x0016

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['customer_nvm_managed', 'algo_config']

fields:

  • [15:0] = crosstalk_compensation_plane_offset_kcps (fixed point 7.9)

◆ VL53L1_ALGO_CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS_HI

#define VL53L1_ALGO_CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS_HI   0x0016

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_ALGO_CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS_LO

#define VL53L1_ALGO_CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS_LO   0x0017

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_ALGO_CROSSTALK_COMPENSATION_VALID_HEIGHT_MM

#define VL53L1_ALGO_CROSSTALK_COMPENSATION_VALID_HEIGHT_MM   0x0039

type: uint8_t
default: 0x14
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'algo_config']

fields:

  • [7:0] = crosstalk_compensation_valid_height_mm

◆ VL53L1_ALGO_CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS

#define VL53L1_ALGO_CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS   0x0018

type: int16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['customer_nvm_managed', 'algo_config']

fields:

  • [15:0] = crosstalk_compensation_x_plane_gradient_kcps (fixed point 5.11)

◆ VL53L1_ALGO_CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS_HI

#define VL53L1_ALGO_CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS_HI   0x0018

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_ALGO_CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS_LO

#define VL53L1_ALGO_CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS_LO   0x0019

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_ALGO_CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS

#define VL53L1_ALGO_CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS   0x001A

type: int16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['customer_nvm_managed', 'algo_config']

fields:

  • [15:0] = crosstalk_compensation_y_plane_gradient_kcps (fixed point 5.11)

◆ VL53L1_ALGO_CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS_HI

#define VL53L1_ALGO_CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS_HI   0x001A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_ALGO_CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS_LO

#define VL53L1_ALGO_CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS_LO   0x001B

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_ALGO_PART_TO_PART_RANGE_OFFSET_MM

#define VL53L1_ALGO_PART_TO_PART_RANGE_OFFSET_MM   0x001E

type: int16_t
default: 0x0000
info:

  • msb = 12
  • lsb = 0
  • i2c_size = 2

groups:
['customer_nvm_managed', 'algo_config']

fields:

  • [12:0] = part_to_part_offset_mm (fixed point 11.2)

◆ VL53L1_ALGO_PART_TO_PART_RANGE_OFFSET_MM_HI

#define VL53L1_ALGO_PART_TO_PART_RANGE_OFFSET_MM_HI   0x001E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_ALGO_PART_TO_PART_RANGE_OFFSET_MM_LO

#define VL53L1_ALGO_PART_TO_PART_RANGE_OFFSET_MM_LO   0x001F

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_ALGO_RANGE_IGNORE_THRESHOLD_MCPS

#define VL53L1_ALGO_RANGE_IGNORE_THRESHOLD_MCPS   0x003C

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['static_config', 'algo_config']

fields:

  • [15:0] = range_ignore_thresh_mcps (fixed point 3.13)

◆ VL53L1_ALGO_RANGE_IGNORE_THRESHOLD_MCPS_HI

#define VL53L1_ALGO_RANGE_IGNORE_THRESHOLD_MCPS_HI   0x003C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_ALGO_RANGE_IGNORE_THRESHOLD_MCPS_LO

#define VL53L1_ALGO_RANGE_IGNORE_THRESHOLD_MCPS_LO   0x003D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_ALGO_RANGE_IGNORE_VALID_HEIGHT_MM

#define VL53L1_ALGO_RANGE_IGNORE_VALID_HEIGHT_MM   0x003E

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'algo_config']

fields:

  • [7:0] = range_ignore_height_mm

◆ VL53L1_ALGO_RANGE_MIN_CLIP

#define VL53L1_ALGO_RANGE_MIN_CLIP   0x003F

type: uint8_t
default: 0x8D
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'algo_config']

fields:

  • [0] = algo_range_min_clip_enable
  • [7:1] = algo_range_min_clip_value_mm

◆ VL53L1_ANA_CONFIG_FAST_OSC_CONFIG_CTRL

#define VL53L1_ANA_CONFIG_FAST_OSC_CONFIG_CTRL   0x0035

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'analog_config']

fields:

  • [0] = osc_config_latch_bypass

◆ VL53L1_ANA_CONFIG_FAST_OSC_FREQ_SET

#define VL53L1_ANA_CONFIG_FAST_OSC_FREQ_SET   0x0115

type: uint8_t
default: OSC_FREQ_SET_DEFAULT
info:

  • msb = 2
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'analog_config']

fields:

  • [2:0] = osc_freq_set

◆ VL53L1_ANA_CONFIG_FAST_OSC_TRIM

#define VL53L1_ANA_CONFIG_FAST_OSC_TRIM   0x0005

type: uint8_t
default: 0x48
info:

  • msb = 6
  • lsb = 0
  • i2c_size = 1

groups:
['static_nvm_managed', 'analog_config']

fields:

  • [6:0] = fast_osc_trim

◆ VL53L1_ANA_CONFIG_FAST_OSC_TRIM_MAX

#define VL53L1_ANA_CONFIG_FAST_OSC_TRIM_MAX   0x0114

type: uint8_t
default: OSC_TRIM_DEFAULT
info:

  • msb = 6
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'analog_config']

fields:

  • [6:0] = osc_trim_max

◆ VL53L1_ANA_CONFIG_OSC_SLOW_CTRL

#define VL53L1_ANA_CONFIG_OSC_SLOW_CTRL   0x00E3

type: uint8_t
default: 0x02
info:

  • msb = 2
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'analog_config']

fields:

  • [0] = osc_slow_en
  • [1] = osc_slow_op_en
  • [2] = osc_slow_freq_sel

◆ VL53L1_ANA_CONFIG_POWERDOWN_GO1

#define VL53L1_ANA_CONFIG_POWERDOWN_GO1   0x00E0

type: uint8_t
default: 0x02
info:

  • msb = 1
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'analog_config']

fields:

  • [0] = go2_ref_bg_disable_avdd
  • [1] = go2_regdvdd1v2_enable_avdd

◆ VL53L1_ANA_CONFIG_REF_BG_CTRL

#define VL53L1_ANA_CONFIG_REF_BG_CTRL   0x00E1

type: uint8_t
default: 0x00
info:

  • msb = 1
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'analog_config']

fields:

  • [0] = go2_ref_overdrvbg_avdd
  • [1] = go2_ref_forcebgison_avdd

◆ VL53L1_ANA_CONFIG_REG_AVDD1V2_SEL

#define VL53L1_ANA_CONFIG_REG_AVDD1V2_SEL   0x0004

type: uint8_t
default: 0x00
info:

  • msb = 1
  • lsb = 0
  • i2c_size = 1

groups:
['static_nvm_managed', 'analog_config']

fields:

  • [1:0] = reg_avdd1v2_sel

◆ VL53L1_ANA_CONFIG_REGDVDD1V2_CTRL

#define VL53L1_ANA_CONFIG_REGDVDD1V2_CTRL   0x00E2

type: uint8_t
default: 0x01
info:

  • msb = 3
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'analog_config']

fields:

  • [0] = go2_regdvdd1v2_sel_pulldown_avdd
  • [1] = go2_regdvdd1v2_sel_boost_avdd
  • [3:2] = go2_regdvdd1v2_selv_avdd

◆ VL53L1_ANA_CONFIG_SPAD_SEL_PSWIDTH

#define VL53L1_ANA_CONFIG_SPAD_SEL_PSWIDTH   0x0033

type: uint8_t
default: 0x02
info:

  • msb = 2
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'analog_config']

fields:

  • [2:0] = spad_sel_pswidth

◆ VL53L1_ANA_CONFIG_VCSEL_PULSE_WIDTH_OFFSET

#define VL53L1_ANA_CONFIG_VCSEL_PULSE_WIDTH_OFFSET   0x0034

type: uint8_t
default: 0x08
info:

  • msb = 4
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'analog_config']

fields:

  • [4:0] = vcsel_pulse_width_offset (fixed point 1.4)

◆ VL53L1_ANA_CONFIG_VCSEL_SELION

#define VL53L1_ANA_CONFIG_VCSEL_SELION   0x0117

type: uint8_t
default: 0x00
info:

  • msb = 5
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'analog_config']

fields:

  • [5:0] = vcsel_selion

◆ VL53L1_ANA_CONFIG_VCSEL_SELION_MAX

#define VL53L1_ANA_CONFIG_VCSEL_SELION_MAX   0x0118

type: uint8_t
default: 0x00
info:

  • msb = 5
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'analog_config']

fields:

  • [5:0] = vcsel_selion_max

◆ VL53L1_ANA_CONFIG_VCSEL_TRIM

#define VL53L1_ANA_CONFIG_VCSEL_TRIM   0x0116

type: uint8_t
default: 0x00
info:

  • msb = 2
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'analog_config']

fields:

  • [2:0] = vcsel_trim

◆ VL53L1_ANA_CONFIG_VHV_REF_SEL_VDDPIX

#define VL53L1_ANA_CONFIG_VHV_REF_SEL_VDDPIX   0x0002

type: uint8_t
default: 0x02
info:

  • msb = 3
  • lsb = 0
  • i2c_size = 1

groups:
['static_nvm_managed', 'analog_config']

fields:

  • [3:0] = ref_sel_vddpix

◆ VL53L1_ANA_CONFIG_VHV_REF_SEL_VQUENCH

#define VL53L1_ANA_CONFIG_VHV_REF_SEL_VQUENCH   0x0003

type: uint8_t
default: 0x10
info:

  • msb = 6
  • lsb = 3
  • i2c_size = 1

groups:
['static_nvm_managed', 'analog_config']

fields:

  • [6:3] = ref_sel_vquench

◆ VL53L1_CAL_CONFIG_REPEAT_RATE

#define VL53L1_CAL_CONFIG_REPEAT_RATE   0x0048

type: uint16_t
default: 0x0000
info:

  • msb = 11
  • lsb = 0
  • i2c_size = 2

groups:
['general_config', 'cal_config']

fields:

  • [11:0] = cal_config_repeat_rate

◆ VL53L1_CAL_CONFIG_REPEAT_RATE_HI

#define VL53L1_CAL_CONFIG_REPEAT_RATE_HI   0x0048

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_CAL_CONFIG_REPEAT_RATE_LO

#define VL53L1_CAL_CONFIG_REPEAT_RATE_LO   0x0049

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_CAL_CONFIG_VCSEL_START

#define VL53L1_CAL_CONFIG_VCSEL_START   0x0047

type: uint8_t
default: 0x0B
info:

  • msb = 6
  • lsb = 0
  • i2c_size = 1

groups:
['general_config', 'cal_config']

fields:

  • [6:0] = cal_config_vcsel_start

◆ VL53L1_CLK_CONFIG

#define VL53L1_CLK_CONFIG   0x04C4

type: uint8_t
default: 0x01
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['']

fields:

  • [0] = clk_mcu_en

◆ VL53L1_CLK_GATING_CTRL

#define VL53L1_CLK_GATING_CTRL   0x0028

type: uint8_t
default: 0x00
info:

  • msb = 3
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'clk_config']

fields:

  • [0] = clk_gate_en_mcu_bank
  • [1] = clk_gate_en_mcu_patch_ctrl
  • [2] = clk_gate_en_mcu_timers
  • [3] = clk_gate_en_mcu_mult_div

◆ VL53L1_DEBUG_CTRL

#define VL53L1_DEBUG_CTRL   0x0026

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'debug_config']

fields:

  • [0] = enable_result_logging

◆ VL53L1_DSS_CALC_MODE_ROI_0

#define VL53L1_DSS_CALC_MODE_ROI_0   0x0F7E

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_mode_roi_0

◆ VL53L1_DSS_CALC_MODE_ROI_1

#define VL53L1_DSS_CALC_MODE_ROI_1   0x0F7F

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_mode_roi_1

◆ VL53L1_DSS_CALC_ROI_CTRL

#define VL53L1_DSS_CALC_ROI_CTRL   0x0F54

type: uint8_t
default: 0x00
info:

  • msb = 1
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [0] = dss_calc_roi_intersect_enable
  • [1] = dss_calc_roi_subtract_enable

◆ VL53L1_DSS_CALC_SPARE_1

#define VL53L1_DSS_CALC_SPARE_1   0x0F55

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_spare_1

◆ VL53L1_DSS_CALC_SPARE_2

#define VL53L1_DSS_CALC_SPARE_2   0x0F56

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_spare_2

◆ VL53L1_DSS_CALC_SPARE_3

#define VL53L1_DSS_CALC_SPARE_3   0x0F57

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_spare_3

◆ VL53L1_DSS_CALC_SPARE_4

#define VL53L1_DSS_CALC_SPARE_4   0x0F58

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_spare_4

◆ VL53L1_DSS_CALC_SPARE_5

#define VL53L1_DSS_CALC_SPARE_5   0x0F59

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_spare_5

◆ VL53L1_DSS_CALC_SPARE_6

#define VL53L1_DSS_CALC_SPARE_6   0x0F5A

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_spare_6

◆ VL53L1_DSS_CALC_SPARE_7

#define VL53L1_DSS_CALC_SPARE_7   0x0F5B

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_spare_7

◆ VL53L1_DSS_CALC_USER_ROI_0

#define VL53L1_DSS_CALC_USER_ROI_0   0x0F7C

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_0

◆ VL53L1_DSS_CALC_USER_ROI_1

#define VL53L1_DSS_CALC_USER_ROI_1   0x0F7D

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_1

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_0

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_0   0x0F5C

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_0

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_1

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_1   0x0F5D

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_1

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_10

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_10   0x0F66

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_10

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_11

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_11   0x0F67

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_11

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_12

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_12   0x0F68

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_12

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_13

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_13   0x0F69

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_13

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_14

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_14   0x0F6A

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_14

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_15

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_15   0x0F6B

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_15

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_16

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_16   0x0F6C

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_16

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_17

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_17   0x0F6D

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_17

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_18

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_18   0x0F6E

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_18

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_19

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_19   0x0F6F

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_19

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_2

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_2   0x0F5E

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_2

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_20

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_20   0x0F70

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_20

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_21

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_21   0x0F71

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_21

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_22

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_22   0x0F72

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_22

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_23

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_23   0x0F73

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_23

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_24

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_24   0x0F74

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_24

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_25

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_25   0x0F75

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_25

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_26

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_26   0x0F76

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_26

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_27

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_27   0x0F77

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_27

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_28

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_28   0x0F78

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_28

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_29

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_29   0x0F79

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_29

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_3

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_3   0x0F5F

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_3

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_30

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_30   0x0F7A

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_30

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_31

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_31   0x0F7B

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_31

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_4

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_4   0x0F60

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_4

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_5

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_5   0x0F61

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_5

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_6

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_6   0x0F62

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_6

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_7

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_7   0x0F63

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_7

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_8

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_8   0x0F64

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_8

◆ VL53L1_DSS_CALC_USER_ROI_SPAD_EN_9

#define VL53L1_DSS_CALC_USER_ROI_SPAD_EN_9   0x0F65

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_calc']

fields:

  • [7:0] = dss_calc_user_roi_spad_en_9

◆ VL53L1_DSS_CONFIG_APERTURE_ATTENUATION

#define VL53L1_DSS_CONFIG_APERTURE_ATTENUATION   0x0057

type: uint8_t
default: 0x33
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['general_config', 'dss_config']

fields:

  • [7:0] = dss_config_aperture_attenuation

◆ VL53L1_DSS_CONFIG_MANUAL_BLOCK_SELECT

#define VL53L1_DSS_CONFIG_MANUAL_BLOCK_SELECT   0x0056

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['general_config', 'dss_config']

fields:

  • [7:0] = dss_config_manual_block_select

◆ VL53L1_DSS_CONFIG_MANUAL_EFFECTIVE_SPADS_SELECT

#define VL53L1_DSS_CONFIG_MANUAL_EFFECTIVE_SPADS_SELECT   0x0054

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['general_config', 'dss_config']

fields:

  • [15:0] = dss_config_manual_effective_spads_select

◆ VL53L1_DSS_CONFIG_MANUAL_EFFECTIVE_SPADS_SELECT_HI

#define VL53L1_DSS_CONFIG_MANUAL_EFFECTIVE_SPADS_SELECT_HI   0x0054

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_DSS_CONFIG_MANUAL_EFFECTIVE_SPADS_SELECT_LO

#define VL53L1_DSS_CONFIG_MANUAL_EFFECTIVE_SPADS_SELECT_LO   0x0055

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_DSS_CONFIG_MAX_SPADS_LIMIT

#define VL53L1_DSS_CONFIG_MAX_SPADS_LIMIT   0x0058

type: uint8_t
default: 0xFF
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['general_config', 'dss_config']

fields:

  • [7:0] = dss_config_max_spads_limit

◆ VL53L1_DSS_CONFIG_MIN_SPADS_LIMIT

#define VL53L1_DSS_CONFIG_MIN_SPADS_LIMIT   0x0059

type: uint8_t
default: 0x01
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['general_config', 'dss_config']

fields:

  • [7:0] = dss_config_min_spads_limit

◆ VL53L1_DSS_CONFIG_ROI_MODE_CONTROL

#define VL53L1_DSS_CONFIG_ROI_MODE_CONTROL   0x004F

type: uint8_t
default: 0x01
info:

  • msb = 2
  • lsb = 0
  • i2c_size = 1

groups:
['general_config', 'dss_config']

fields:

  • [1:0] = dss_config_input_mode
  • [2] = calculate_roi_enable

◆ VL53L1_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS

#define VL53L1_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS   0x0024

type: uint16_t
default: 0x0380
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['static_config', 'dss_config']

fields:

  • [15:0] = dss_config_target_total_rate_mcps (fixed point 9.7)

◆ VL53L1_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_HI

#define VL53L1_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_HI   0x0024

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_LO

#define VL53L1_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_LO   0x0025

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_DSS_RESULT_ENABLED_BLOCKS

#define VL53L1_DSS_RESULT_ENABLED_BLOCKS   0x0F8C

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'dss_results']

fields:

  • [7:0] = dss_result_enabled_blocks

◆ VL53L1_DSS_RESULT_NUM_REQUESTED_SPADS

#define VL53L1_DSS_RESULT_NUM_REQUESTED_SPADS   0x0F8E

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['patch_results', 'dss_results']

fields:

  • [15:0] = dss_result_num_requested_spads (fixed point 8.8)

◆ VL53L1_DSS_RESULT_NUM_REQUESTED_SPADS_HI

#define VL53L1_DSS_RESULT_NUM_REQUESTED_SPADS_HI   0x0F8E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_DSS_RESULT_NUM_REQUESTED_SPADS_LO

#define VL53L1_DSS_RESULT_NUM_REQUESTED_SPADS_LO   0x0F8F

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_DSS_RESULT_TOTAL_RATE_PER_SPAD

#define VL53L1_DSS_RESULT_TOTAL_RATE_PER_SPAD   0x0F8A

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['patch_results', 'dss_results']

fields:

  • [15:0] = dss_result_total_rate_per_spad

◆ VL53L1_DSS_RESULT_TOTAL_RATE_PER_SPAD_HI

#define VL53L1_DSS_RESULT_TOTAL_RATE_PER_SPAD_HI   0x0F8A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_DSS_RESULT_TOTAL_RATE_PER_SPAD_LO

#define VL53L1_DSS_RESULT_TOTAL_RATE_PER_SPAD_LO   0x0F8B

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_FIRMWARE_CAL_REPEAT_RATE_COUNTER

#define VL53L1_FIRMWARE_CAL_REPEAT_RATE_COUNTER   0x00E8

type: uint16_t
default: 0x0000
info:

  • msb = 11
  • lsb = 0
  • i2c_size = 2

groups:
['debug_results', 'firmware_status']

fields:

  • [11:0] = firmware_cal_repeat_rate

◆ VL53L1_FIRMWARE_CAL_REPEAT_RATE_COUNTER_HI

#define VL53L1_FIRMWARE_CAL_REPEAT_RATE_COUNTER_HI   0x00E8

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_FIRMWARE_CAL_REPEAT_RATE_COUNTER_LO

#define VL53L1_FIRMWARE_CAL_REPEAT_RATE_COUNTER_LO   0x00E9

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_FIRMWARE_ENABLE

#define VL53L1_FIRMWARE_ENABLE   0x0085

type: uint8_t
default: 0x01
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['system_control', 'firmware_ctrl']

fields:

  • [0] = firmware_enable

◆ VL53L1_FIRMWARE_HISTOGRAM_BIN

#define VL53L1_FIRMWARE_HISTOGRAM_BIN   0x00EA

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_FIRMWARE_INTERNAL_STREAM_COUNT_DIV

#define VL53L1_FIRMWARE_INTERNAL_STREAM_COUNT_DIV   0x0F46

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['fw_internal']

fields:

  • [7:0] = fw_internal_stream_count_div

◆ VL53L1_FIRMWARE_INTERNAL_STREAM_COUNTER_VAL

#define VL53L1_FIRMWARE_INTERNAL_STREAM_COUNTER_VAL   0x0F47

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['fw_internal']

fields:

  • [7:0] = fw_internal_stream_counter_val

◆ VL53L1_FIRMWARE_MODE_STATUS

#define VL53L1_FIRMWARE_MODE_STATUS   0x00E6

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'firmware_status']

fields:

  • [7:0] = firmware_mode_status

◆ VL53L1_FIRMWARE_SECONDARY_MODE_STATUS

#define VL53L1_FIRMWARE_SECONDARY_MODE_STATUS   0x00E7

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'firmware_status']

fields:

  • [7:0] = fw_secondary_mode_status

◆ VL53L1_FIRMWARE_SYSTEM_STATUS

#define VL53L1_FIRMWARE_SYSTEM_STATUS   0x00E5

type: uint8_t
default: 0x02
info:

  • msb = 1
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'firmware_status']

fields:

  • [0] = firmware_bootup
  • [1] = firmware_first_range

◆ VL53L1_GLOBAL_CONFIG_REF_EN_START_SELECT

#define VL53L1_GLOBAL_CONFIG_REF_EN_START_SELECT   0x0013

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['customer_nvm_managed', 'ref_spad_start']

fields:

  • [7:0] = ref_en_start_select

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_REF_0

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_REF_0   0x000D

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['customer_nvm_managed', 'ref_spad_en']

fields:

  • [7:0] = spad_enables_ref_0

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_REF_1

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_REF_1   0x000E

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['customer_nvm_managed', 'ref_spad_en']

fields:

  • [7:0] = spad_enables_ref_1

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_REF_2

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_REF_2   0x000F

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['customer_nvm_managed', 'ref_spad_en']

fields:

  • [7:0] = spad_enables_ref_2

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_REF_3

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_REF_3   0x0010

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['customer_nvm_managed', 'ref_spad_en']

fields:

  • [7:0] = spad_enables_ref_3

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_REF_4

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_REF_4   0x0011

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['customer_nvm_managed', 'ref_spad_en']

fields:

  • [7:0] = spad_enables_ref_4

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_REF_5

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_REF_5   0x0012

type: uint8_t
default: 0x00
info:

  • msb = 3
  • lsb = 0
  • i2c_size = 1

groups:
['customer_nvm_managed', 'ref_spad_en']

fields:

  • [3:0] = spad_enables_ref_5

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_0

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_0   0x011E

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_0

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_1

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_1   0x011F

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_1

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_10

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_10   0x0128

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_10

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_11

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_11   0x0129

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_11

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_12

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_12   0x012A

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_12

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_13

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_13   0x012B

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_13

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_14

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_14   0x012C

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_14

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_15

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_15   0x012D

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_15

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_16

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_16   0x012E

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_16

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_17

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_17   0x012F

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_17

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_18

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_18   0x0130

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_18

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_19

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_19   0x0131

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_19

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_2

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_2   0x0120

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_2

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_20

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_20   0x0132

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_20

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_21

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_21   0x0133

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_21

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_22

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_22   0x0134

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_22

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_23

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_23   0x0135

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_23

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_24

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_24   0x0136

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_24

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_25

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_25   0x0137

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_25

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_26

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_26   0x0138

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_26

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_27

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_27   0x0139

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_27

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_28

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_28   0x013A

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_28

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_29

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_29   0x013B

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_29

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_3

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_3   0x0121

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_3

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_30

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_30   0x013C

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_30

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_31

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_31   0x013D

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_31

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_4

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_4   0x0122

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_4

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_5

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_5   0x0123

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_5

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_6

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_6   0x0124

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_6

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_7

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_7   0x0125

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_7

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_8

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_8   0x0126

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_8

◆ VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_9

#define VL53L1_GLOBAL_CONFIG_SPAD_ENABLES_RTN_9   0x0127

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'ret_spad_config']

fields:

  • [7:0] = spad_enables_rtn_9

◆ VL53L1_GLOBAL_CONFIG_STREAM_DIVIDER

#define VL53L1_GLOBAL_CONFIG_STREAM_DIVIDER   0x0045

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['general_config', 'roi_config']

fields:

  • [7:0] = stream_count_internal_div

◆ VL53L1_GLOBAL_CONFIG_VCSEL_WIDTH

#define VL53L1_GLOBAL_CONFIG_VCSEL_WIDTH   0x004A

type: uint8_t
default: 0x02
info:

  • msb = 6
  • lsb = 0
  • i2c_size = 1

groups:
['general_config', 'global_config']

fields:

  • [6:0] = global_config_vcsel_width

◆ VL53L1_GO2_HOST_BANK_ACCESS_OVERRIDE

#define VL53L1_GO2_HOST_BANK_ACCESS_OVERRIDE   0x0300

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_GPH_CONFIG_STREAM_COUNT_UPDATE_VALUE

#define VL53L1_GPH_CONFIG_STREAM_COUNT_UPDATE_VALUE   0x0044

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['general_config', 'roi_config']

fields:

  • [7:0] = stream_count_update_value

◆ VL53L1_GPH_DSS_CONFIG_MANUAL_BLOCK_SELECT

#define VL53L1_GPH_DSS_CONFIG_MANUAL_BLOCK_SELECT   0x0F32

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['gph_static_config', 'dss_config']

fields:

  • [7:0] = gph_dss_config_manual_block_select

◆ VL53L1_GPH_DSS_CONFIG_MANUAL_EFFECTIVE_SPADS_SELECT

#define VL53L1_GPH_DSS_CONFIG_MANUAL_EFFECTIVE_SPADS_SELECT   0x0F30

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['gph_static_config', 'dss_config']

fields:

  • [15:0] = gph_dss_config_manual_effective_spads_select

◆ VL53L1_GPH_DSS_CONFIG_MANUAL_EFFECTIVE_SPADS_SELECT_HI

#define VL53L1_GPH_DSS_CONFIG_MANUAL_EFFECTIVE_SPADS_SELECT_HI   0x0F30

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_GPH_DSS_CONFIG_MANUAL_EFFECTIVE_SPADS_SELECT_LO

#define VL53L1_GPH_DSS_CONFIG_MANUAL_EFFECTIVE_SPADS_SELECT_LO   0x0F31

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_GPH_DSS_CONFIG_MAX_SPADS_LIMIT

#define VL53L1_GPH_DSS_CONFIG_MAX_SPADS_LIMIT   0x0F33

type: uint8_t
default: 0xFF
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['gph_static_config', 'dss_config']

fields:

  • [7:0] = gph_dss_config_max_spads_limit

◆ VL53L1_GPH_DSS_CONFIG_MIN_SPADS_LIMIT

#define VL53L1_GPH_DSS_CONFIG_MIN_SPADS_LIMIT   0x0F34

type: uint8_t
default: 0x01
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['gph_static_config', 'dss_config']

fields:

  • [7:0] = gph_dss_config_min_spads_limit

◆ VL53L1_GPH_DSS_CONFIG_ROI_MODE_CONTROL

#define VL53L1_GPH_DSS_CONFIG_ROI_MODE_CONTROL   0x0F2F

type: uint8_t
default: 0x01
info:

  • msb = 2
  • lsb = 0
  • i2c_size = 1

groups:
['gph_static_config', 'dss_config']

fields:

  • [1:0] = gph_dss_config_input_mode
  • [2] = gph_calculate_roi_enable

◆ VL53L1_GPH_GPH_ID

#define VL53L1_GPH_GPH_ID   0x00FB

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'gph_actual']

fields:

  • [0] = shadow_gph_id

◆ VL53L1_GPH_MM_CONFIG_TIMEOUT_MACROP_A_HI

#define VL53L1_GPH_MM_CONFIG_TIMEOUT_MACROP_A_HI   0x0F36

type: uint8_t
default: 0x00
info:

  • msb = 3
  • lsb = 0
  • i2c_size = 1

groups:
['gph_timing_config', 'mm_config']

fields:

  • [3:0] = gph_mm_config_config_timeout_macrop_a_hi

◆ VL53L1_GPH_MM_CONFIG_TIMEOUT_MACROP_A_LO

#define VL53L1_GPH_MM_CONFIG_TIMEOUT_MACROP_A_LO   0x0F37

type: uint8_t
default: 0x06
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['gph_timing_config', 'mm_config']

fields:

  • [7:0] = gph_mm_config_config_timeout_macrop_a_lo

◆ VL53L1_GPH_MM_CONFIG_TIMEOUT_MACROP_B_HI

#define VL53L1_GPH_MM_CONFIG_TIMEOUT_MACROP_B_HI   0x0F38

type: uint8_t
default: 0x00
info:

  • msb = 3
  • lsb = 0
  • i2c_size = 1

groups:
['gph_timing_config', 'mm_config']

fields:

  • [3:0] = gph_mm_config_config_timeout_macrop_b_hi

◆ VL53L1_GPH_MM_CONFIG_TIMEOUT_MACROP_B_LO

#define VL53L1_GPH_MM_CONFIG_TIMEOUT_MACROP_B_LO   0x0F39

type: uint8_t
default: 0x06
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['gph_timing_config', 'mm_config']

fields:

  • [7:0] = gph_mm_config_config_timeout_macrop_b_lo

◆ VL53L1_GPH_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT_MCPS

#define VL53L1_GPH_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT_MCPS   0x0F42

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['gph_timing_config', 'range_config']

fields:

  • [15:0] = gph_range_config_min_count_rate_rtn_limit_mcps (fixed point 9.7)

◆ VL53L1_GPH_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI

#define VL53L1_GPH_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI   0x0F42

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_GPH_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO

#define VL53L1_GPH_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO   0x0F43

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_GPH_RANGE_CONFIG_SIGMA_THRESH

#define VL53L1_GPH_RANGE_CONFIG_SIGMA_THRESH   0x0F40

type: uint16_t
default: 0x0080
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['gph_timing_config', 'range_config']

fields:

  • [15:0] = gph_range_config_sigma_thresh (fixed point 14.2)

◆ VL53L1_GPH_RANGE_CONFIG_SIGMA_THRESH_HI

#define VL53L1_GPH_RANGE_CONFIG_SIGMA_THRESH_HI   0x0F40

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_GPH_RANGE_CONFIG_SIGMA_THRESH_LO

#define VL53L1_GPH_RANGE_CONFIG_SIGMA_THRESH_LO   0x0F41

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_GPH_RANGE_CONFIG_TIMEOUT_MACROP_A_HI

#define VL53L1_GPH_RANGE_CONFIG_TIMEOUT_MACROP_A_HI   0x0F3A

type: uint8_t
default: 0x01
info:

  • msb = 3
  • lsb = 0
  • i2c_size = 1

groups:
['gph_timing_config', 'range_config']

fields:

  • [3:0] = gph_range_timeout_overall_periods_macrop_a_hi

◆ VL53L1_GPH_RANGE_CONFIG_TIMEOUT_MACROP_A_LO

#define VL53L1_GPH_RANGE_CONFIG_TIMEOUT_MACROP_A_LO   0x0F3B

type: uint8_t
default: 0x92
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['gph_timing_config', 'range_config']

fields:

  • [7:0] = gph_range_timeout_overall_periods_macrop_a_lo

◆ VL53L1_GPH_RANGE_CONFIG_TIMEOUT_MACROP_B_HI

#define VL53L1_GPH_RANGE_CONFIG_TIMEOUT_MACROP_B_HI   0x0F3E

type: uint8_t
default: 0x01
info:

  • msb = 3
  • lsb = 0
  • i2c_size = 1

groups:
['gph_timing_config', 'range_config']

fields:

  • [3:0] = gph_range_timeout_overall_periods_macrop_b_hi

◆ VL53L1_GPH_RANGE_CONFIG_TIMEOUT_MACROP_B_LO

#define VL53L1_GPH_RANGE_CONFIG_TIMEOUT_MACROP_B_LO   0x0F3F

type: uint8_t
default: 0x92
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['gph_timing_config', 'range_config']

fields:

  • [7:0] = gph_range_timeout_overall_periods_macrop_b_lo

◆ VL53L1_GPH_RANGE_CONFIG_VALID_PHASE_HIGH

#define VL53L1_GPH_RANGE_CONFIG_VALID_PHASE_HIGH   0x0F45

type: uint8_t
default: 0x80
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['gph_timing_config', 'range_config']

fields:

  • [7:0] = gph_range_config_valid_phase_high (fixed point 5.3)

◆ VL53L1_GPH_RANGE_CONFIG_VALID_PHASE_LOW

#define VL53L1_GPH_RANGE_CONFIG_VALID_PHASE_LOW   0x0F44

type: uint8_t
default: 0x08
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['gph_timing_config', 'range_config']

fields:

  • [7:0] = gph_range_config_valid_phase_low (fixed point 5.3)

◆ VL53L1_GPH_RANGE_CONFIG_VCSEL_PERIOD_A

#define VL53L1_GPH_RANGE_CONFIG_VCSEL_PERIOD_A   0x0F3C

type: uint8_t
default: 0x0B
info:

  • msb = 5
  • lsb = 0
  • i2c_size = 1

groups:
['gph_timing_config', 'range_config']

fields:

  • [5:0] = gph_range_config_vcsel_period_a

◆ VL53L1_GPH_RANGE_CONFIG_VCSEL_PERIOD_B

#define VL53L1_GPH_RANGE_CONFIG_VCSEL_PERIOD_B   0x0F3D

type: uint8_t
default: 0x09
info:

  • msb = 5
  • lsb = 0
  • i2c_size = 1

groups:
['gph_timing_config', 'range_config']

fields:

  • [5:0] = gph_range_config_vcsel_period_b

◆ VL53L1_GPH_ROI_CONFIG_USER_ROI_CENTRE_SPAD

#define VL53L1_GPH_ROI_CONFIG_USER_ROI_CENTRE_SPAD   0x00F8

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'gph_actual']

fields:

  • [7:0] = shadow_user_roi_center_spad_q0

◆ VL53L1_GPH_ROI_CONFIG_USER_ROI_REQUESTED_GLOBAL_XY_SIZE

#define VL53L1_GPH_ROI_CONFIG_USER_ROI_REQUESTED_GLOBAL_XY_SIZE   0x00F9

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'gph_actual']

fields:

  • [7:0] = shadow_user_roi_requested_global_xy_size

◆ VL53L1_GPH_SD_CONFIG_FIRST_ORDER_SELECT

#define VL53L1_GPH_SD_CONFIG_FIRST_ORDER_SELECT   0x00F6

type: uint8_t
default: 0x00
info:

  • msb = 1
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'gph_actual']

fields:

  • [0] = shadow_sd_config_first_order_select_rtn
  • [1] = shadow_sd_config_first_order_select_ref

◆ VL53L1_GPH_SD_CONFIG_INITIAL_PHASE_SD0

#define VL53L1_GPH_SD_CONFIG_INITIAL_PHASE_SD0   0x00F4

type: uint8_t
default: 0x03
info:

  • msb = 6
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'gph_actual']

fields:

  • [6:0] = shadow_sd_config_initial_phase_sd0

◆ VL53L1_GPH_SD_CONFIG_INITIAL_PHASE_SD1

#define VL53L1_GPH_SD_CONFIG_INITIAL_PHASE_SD1   0x00F5

type: uint8_t
default: 0x03
info:

  • msb = 6
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'gph_actual']

fields:

  • [6:0] = shadow_sd_config_initial_phase_sd1

◆ VL53L1_GPH_SD_CONFIG_QUANTIFIER

#define VL53L1_GPH_SD_CONFIG_QUANTIFIER   0x00F7

type: uint8_t
default: 0x00
info:

  • msb = 3
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'gph_actual']

fields:

  • [3:0] = shadow_sd_config_quantifier

◆ VL53L1_GPH_SD_CONFIG_WOI_SD0

#define VL53L1_GPH_SD_CONFIG_WOI_SD0   0x00F2

type: uint8_t
default: 0x04
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'gph_actual']

fields:

  • [7:0] = shadow_sd_config_woi_sd0

◆ VL53L1_GPH_SD_CONFIG_WOI_SD1

#define VL53L1_GPH_SD_CONFIG_WOI_SD1   0x00F3

type: uint8_t
default: 0x04
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'gph_actual']

fields:

  • [7:0] = shadow_sd_config_woi_sd1

◆ VL53L1_GPH_SPARE_0

#define VL53L1_GPH_SPARE_0   0x00F1

type: uint8_t
default: 0x00
info:

  • msb = 2
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'gph_actual']

fields:

  • [0] = fw_safe_to_disable
  • [1] = shadow_spare_0
  • [2] = shadow_spare_1

◆ VL53L1_GPH_SYSTEM_ENABLE_XTALK_PER_QUADRANT

#define VL53L1_GPH_SYSTEM_ENABLE_XTALK_PER_QUADRANT   0x00F0

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'gph_actual']

fields:

  • [0] = shadow_enable_xtalk_per_quadrant

◆ VL53L1_GPH_SYSTEM_INTERRUPT_CONFIG_GPIO

#define VL53L1_GPH_SYSTEM_INTERRUPT_CONFIG_GPIO   0x0F28

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['gph_general_config', 'gph_config']

fields:

  • [1:0] = gph_int_mode_distance
  • [3:2] = gph_int_mode_rate
  • [4] = gph_int_spare
  • [5] = gph_int_new_measure_ready
  • [6] = gph_int_no_target_en
  • [7] = gph_int_combined_mode

◆ VL53L1_GPH_SYSTEM_SEQUENCE_CONFIG

#define VL53L1_GPH_SYSTEM_SEQUENCE_CONFIG   0x00FA

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'gph_actual']

fields:

  • [0] = shadow_sequence_vhv_en
  • [1] = shadow_sequence_phasecal_en
  • [2] = shadow_sequence_reference_phase_en
  • [3] = shadow_sequence_dss1_en
  • [4] = shadow_sequence_dss2_en
  • [5] = shadow_sequence_mm1_en
  • [6] = shadow_sequence_mm2_en
  • [7] = shadow_sequence_range_en

◆ VL53L1_GPH_SYSTEM_THRESH_HIGH

#define VL53L1_GPH_SYSTEM_THRESH_HIGH   0x00EC

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['debug_results', 'gph_actual']

fields:

  • [15:0] = shadow_thresh_high

◆ VL53L1_GPH_SYSTEM_THRESH_HIGH_HI

#define VL53L1_GPH_SYSTEM_THRESH_HIGH_HI   0x00EC

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_GPH_SYSTEM_THRESH_HIGH_LO

#define VL53L1_GPH_SYSTEM_THRESH_HIGH_LO   0x00ED

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_GPH_SYSTEM_THRESH_LOW

#define VL53L1_GPH_SYSTEM_THRESH_LOW   0x00EE

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['debug_results', 'gph_actual']

fields:

  • [15:0] = shadow_thresh_low

◆ VL53L1_GPH_SYSTEM_THRESH_LOW_HI

#define VL53L1_GPH_SYSTEM_THRESH_LOW_HI   0x00EE

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_GPH_SYSTEM_THRESH_LOW_LO

#define VL53L1_GPH_SYSTEM_THRESH_LOW_LO   0x00EF

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_GPH_SYSTEM_THRESH_RATE_HIGH

#define VL53L1_GPH_SYSTEM_THRESH_RATE_HIGH   0x0F24

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['gph_general_config', 'dss_config']

fields:

  • [15:0] = gph_system_thresh_rate_high (fixed point 9.7)

◆ VL53L1_GPH_SYSTEM_THRESH_RATE_HIGH_HI

#define VL53L1_GPH_SYSTEM_THRESH_RATE_HIGH_HI   0x0F24

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_GPH_SYSTEM_THRESH_RATE_HIGH_LO

#define VL53L1_GPH_SYSTEM_THRESH_RATE_HIGH_LO   0x0F25

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_GPH_SYSTEM_THRESH_RATE_LOW

#define VL53L1_GPH_SYSTEM_THRESH_RATE_LOW   0x0F26

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['gph_general_config', 'dss_config']

fields:

  • [15:0] = gph_system_thresh_rate_low (fixed point 9.7)

◆ VL53L1_GPH_SYSTEM_THRESH_RATE_LOW_HI

#define VL53L1_GPH_SYSTEM_THRESH_RATE_LOW_HI   0x0F26

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_GPH_SYSTEM_THRESH_RATE_LOW_LO

#define VL53L1_GPH_SYSTEM_THRESH_RATE_LOW_LO   0x0F27

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_GPIO_FIO_HV_STATUS

#define VL53L1_GPIO_FIO_HV_STATUS   0x0032

type: uint8_t
default: 0x00
info:

  • msb = 1
  • lsb = 1
  • i2c_size = 1

groups:
['static_config', 'gpio_config']

fields:

  • [1] = gpio_fio_hv

◆ VL53L1_GPIO_HV_MUX_CTRL

#define VL53L1_GPIO_HV_MUX_CTRL   0x0030

type: uint8_t
default: 0x11
info:

  • msb = 4
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'gpio_config']

fields:

  • [3:0] = gpio_mux_select_hv
  • [4] = gpio_mux_active_high_hv

◆ VL53L1_GPIO_HV_PAD_CTRL

#define VL53L1_GPIO_HV_PAD_CTRL   0x002F

type: uint8_t
default: 0x00
info:

  • msb = 1
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'gpio_config']

fields:

  • [0] = gpio_extsup_hv
  • [1] = gpio_vmodeint_hv

◆ VL53L1_GPIO_LV_MUX_CTRL

#define VL53L1_GPIO_LV_MUX_CTRL   0x04CC

type: uint8_t
default: 0x08
info:

  • msb = 4
  • lsb = 0
  • i2c_size = 1

groups:
['']

fields:

  • [3:0] = gpio_mux_select_lv
  • [4] = gpio_mux_active_high_lv

◆ VL53L1_GPIO_LV_PAD_CTRL

#define VL53L1_GPIO_LV_PAD_CTRL   0x04CD

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['']

fields:

  • [0] = gpio_extsup_lv

◆ VL53L1_GPIO_TIO_HV_STATUS

#define VL53L1_GPIO_TIO_HV_STATUS   0x0031

type: uint8_t
default: 0x02
info:

  • msb = 1
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'gpio_config']

fields:

  • [0] = gpio_tio_hv
  • [1] = fresh_out_of_reset

◆ VL53L1_HOST_IF_STATUS

#define VL53L1_HOST_IF_STATUS   0x002C

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'system_status']

fields:

  • [0] = host_interface

◆ VL53L1_HOST_IF_STATUS_GO1

#define VL53L1_HOST_IF_STATUS_GO1   0x04D5

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['']

fields:

  • [0] = host_interface_lv

◆ VL53L1_I2C_SLAVE_DEVICE_ADDRESS

#define VL53L1_I2C_SLAVE_DEVICE_ADDRESS   0x0001

type: uint8_t
default: EWOK_I2C_DEV_ADDR_DEFAULT
info:

  • msb = 6
  • lsb = 0
  • i2c_size = 1

groups:
['static_nvm_managed', 'system_config']

fields:

  • [6:0] = i2c_slave_device_address

◆ VL53L1_IDENTIFICATION_MODEL_ID

#define VL53L1_IDENTIFICATION_MODEL_ID   0x010F

type: uint8_t
default: 0xEA
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'identification']

fields:

  • [7:0] = model_id

◆ VL53L1_IDENTIFICATION_MODULE_ID

#define VL53L1_IDENTIFICATION_MODULE_ID   0x0112

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['nvm_copy_data', 'identification']

fields:

  • [15:0] = module_id

◆ VL53L1_IDENTIFICATION_MODULE_ID_HI

#define VL53L1_IDENTIFICATION_MODULE_ID_HI   0x0112

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_IDENTIFICATION_MODULE_ID_LO

#define VL53L1_IDENTIFICATION_MODULE_ID_LO   0x0113

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_IDENTIFICATION_MODULE_TYPE

#define VL53L1_IDENTIFICATION_MODULE_TYPE   0x0110

type: uint8_t
default: 0xAA
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'identification']

fields:

  • [7:0] = module_type

◆ VL53L1_IDENTIFICATION_REVISION_ID

#define VL53L1_IDENTIFICATION_REVISION_ID   0x0111

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'identification']

fields:

  • [3:0] = nvm_revision_id
  • [7:4] = mask_revision_id

◆ VL53L1_INTERRUPT_MANAGER_CLEAR

#define VL53L1_INTERRUPT_MANAGER_CLEAR   0x00FE

type: uint8_t
default: 0x00
info:

  • msb = 4
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'interrupt_manager']

fields:

  • [0] = interrupt_clear_single_shot
  • [1] = interrupt_clear_back_to_back
  • [2] = interrupt_clear_timed
  • [3] = interrupt_clear_abort
  • [4] = interrupt_clear_test

◆ VL53L1_INTERRUPT_MANAGER_ENABLES

#define VL53L1_INTERRUPT_MANAGER_ENABLES   0x00FD

type: uint8_t
default: 0x00
info:

  • msb = 4
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'interrupt_manager']

fields:

  • [0] = interrupt_enable_single_shot
  • [1] = interrupt_enable_back_to_back
  • [2] = interrupt_enable_timed
  • [3] = interrupt_enable_abort
  • [4] = interrupt_enable_test

◆ VL53L1_INTERRUPT_MANAGER_STATUS

#define VL53L1_INTERRUPT_MANAGER_STATUS   0x00FF

type: uint8_t
default: 0x00
info:

  • msb = 4
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'interrupt_manager']

fields:

  • [0] = interrupt_status_single_shot
  • [1] = interrupt_status_back_to_back
  • [2] = interrupt_status_timed
  • [3] = interrupt_status_abort
  • [4] = interrupt_status_test

◆ VL53L1_INTERRUPT_SCHEDULER_DATA_OUT

#define VL53L1_INTERRUPT_SCHEDULER_DATA_OUT   0x0108

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['debug_results', 'debug_timer']

fields:

  • [31:0] = interrupt_scheduler_data_out

◆ VL53L1_INTERRUPT_SCHEDULER_DATA_OUT_0

#define VL53L1_INTERRUPT_SCHEDULER_DATA_OUT_0   0x010B

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_INTERRUPT_SCHEDULER_DATA_OUT_1

#define VL53L1_INTERRUPT_SCHEDULER_DATA_OUT_1   0x010A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_INTERRUPT_SCHEDULER_DATA_OUT_2

#define VL53L1_INTERRUPT_SCHEDULER_DATA_OUT_2   0x0109

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_INTERRUPT_SCHEDULER_DATA_OUT_3

#define VL53L1_INTERRUPT_SCHEDULER_DATA_OUT_3   0x0108

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_LASER_SAFETY_CLIP

#define VL53L1_LASER_SAFETY_CLIP   0x011C

type: uint8_t
default: 0x02
info:

  • msb = 5
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'laser_safety']

fields:

  • [5:0] = vcsel_pulse_width_clip

◆ VL53L1_LASER_SAFETY_KEY

#define VL53L1_LASER_SAFETY_KEY   0x011A

type: uint8_t
default: 0x00
info:

  • msb = 6
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'laser_safety']

fields:

  • [6:0] = laser_safety_key

◆ VL53L1_LASER_SAFETY_KEY_RO

#define VL53L1_LASER_SAFETY_KEY_RO   0x011B

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'laser_safety']

fields:

  • [0] = laser_safety_key_ro

◆ VL53L1_LASER_SAFETY_MULT

#define VL53L1_LASER_SAFETY_MULT   0x011D

type: uint8_t
default: 0x32
info:

  • msb = 5
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'laser_safety']

fields:

  • [5:0] = vcsel_pulse_width_mult

◆ VL53L1_MCU_CLK_GATING_CTRL

#define VL53L1_MCU_CLK_GATING_CTRL   0x04D8

type: uint8_t
default: 0x00
info:

  • msb = 3
  • lsb = 0
  • i2c_size = 1

groups:
['']

fields:

  • [0] = clk_gate_en_go1_mcu_bank
  • [1] = clk_gate_en_go1_mcu_patch_ctrl
  • [2] = clk_gate_en_go1_mcu_timers
  • [3] = clk_gate_en_go1_mcu_mult_div

◆ VL53L1_MCU_GENERAL_PURPOSE_GP_0

#define VL53L1_MCU_GENERAL_PURPOSE_GP_0   0x042C

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['']

fields:

  • [7:0] = mcu_gp_0

◆ VL53L1_MCU_GENERAL_PURPOSE_GP_1

#define VL53L1_MCU_GENERAL_PURPOSE_GP_1   0x042D

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['']

fields:

  • [7:0] = mcu_gp_1

◆ VL53L1_MCU_GENERAL_PURPOSE_GP_2

#define VL53L1_MCU_GENERAL_PURPOSE_GP_2   0x042E

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['']

fields:

  • [7:0] = mcu_gp_2

◆ VL53L1_MCU_GENERAL_PURPOSE_GP_3

#define VL53L1_MCU_GENERAL_PURPOSE_GP_3   0x042F

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['']

fields:

  • [7:0] = mcu_gp_3

◆ VL53L1_MCU_RANGE_CALC_ALGO_ACCUM_PHASE

#define VL53L1_MCU_RANGE_CALC_ALGO_ACCUM_PHASE   0x0440

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['']

fields:

  • [31:0] = algo_accum_phase

◆ VL53L1_MCU_RANGE_CALC_ALGO_ACCUM_PHASE_0

#define VL53L1_MCU_RANGE_CALC_ALGO_ACCUM_PHASE_0   0x0443

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_ALGO_ACCUM_PHASE_1

#define VL53L1_MCU_RANGE_CALC_ALGO_ACCUM_PHASE_1   0x0442

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_ALGO_ACCUM_PHASE_2

#define VL53L1_MCU_RANGE_CALC_ALGO_ACCUM_PHASE_2   0x0441

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_ALGO_ACCUM_PHASE_3

#define VL53L1_MCU_RANGE_CALC_ALGO_ACCUM_PHASE_3   0x0440

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_ALGO_ADJUST_VCSEL_PERIOD

#define VL53L1_MCU_RANGE_CALC_ALGO_ADJUST_VCSEL_PERIOD   0x044E

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['']

fields:

  • [15:0] = algo_adjust_vcsel_period

◆ VL53L1_MCU_RANGE_CALC_ALGO_ADJUST_VCSEL_PERIOD_HI

#define VL53L1_MCU_RANGE_CALC_ALGO_ADJUST_VCSEL_PERIOD_HI   0x044E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_ALGO_ADJUST_VCSEL_PERIOD_LO

#define VL53L1_MCU_RANGE_CALC_ALGO_ADJUST_VCSEL_PERIOD_LO   0x044F

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_ALGO_AMBIENT_EVENTS

#define VL53L1_MCU_RANGE_CALC_ALGO_AMBIENT_EVENTS   0x0448

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['']

fields:

  • [31:0] = algo_ambient_events

◆ VL53L1_MCU_RANGE_CALC_ALGO_AMBIENT_EVENTS_0

#define VL53L1_MCU_RANGE_CALC_ALGO_AMBIENT_EVENTS_0   0x044B

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_ALGO_AMBIENT_EVENTS_1

#define VL53L1_MCU_RANGE_CALC_ALGO_AMBIENT_EVENTS_1   0x044A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_ALGO_AMBIENT_EVENTS_2

#define VL53L1_MCU_RANGE_CALC_ALGO_AMBIENT_EVENTS_2   0x0449

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_ALGO_AMBIENT_EVENTS_3

#define VL53L1_MCU_RANGE_CALC_ALGO_AMBIENT_EVENTS_3   0x0448

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_ALGO_SIGNAL_EVENTS

#define VL53L1_MCU_RANGE_CALC_ALGO_SIGNAL_EVENTS   0x0444

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['']

fields:

  • [31:0] = algo_signal_events

◆ VL53L1_MCU_RANGE_CALC_ALGO_SIGNAL_EVENTS_0

#define VL53L1_MCU_RANGE_CALC_ALGO_SIGNAL_EVENTS_0   0x0447

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_ALGO_SIGNAL_EVENTS_1

#define VL53L1_MCU_RANGE_CALC_ALGO_SIGNAL_EVENTS_1   0x0446

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_ALGO_SIGNAL_EVENTS_2

#define VL53L1_MCU_RANGE_CALC_ALGO_SIGNAL_EVENTS_2   0x0445

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_ALGO_SIGNAL_EVENTS_3

#define VL53L1_MCU_RANGE_CALC_ALGO_SIGNAL_EVENTS_3   0x0444

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_ALGO_TOTAL_PERIODS

#define VL53L1_MCU_RANGE_CALC_ALGO_TOTAL_PERIODS   0x043E

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['']

fields:

  • [15:0] = algo_total_periods

◆ VL53L1_MCU_RANGE_CALC_ALGO_TOTAL_PERIODS_HI

#define VL53L1_MCU_RANGE_CALC_ALGO_TOTAL_PERIODS_HI   0x043E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_ALGO_TOTAL_PERIODS_LO

#define VL53L1_MCU_RANGE_CALC_ALGO_TOTAL_PERIODS_LO   0x043F

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_ALGO_VCSEL_PERIOD

#define VL53L1_MCU_RANGE_CALC_ALGO_VCSEL_PERIOD   0x043C

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['']

fields:

  • [7:0] = algo_vcsel_period

◆ VL53L1_MCU_RANGE_CALC_AMBIENT_DURATION_PRE_CALC

#define VL53L1_MCU_RANGE_CALC_AMBIENT_DURATION_PRE_CALC   0x0438

type: uint16_t
default: 0x0000
info:

  • msb = 13
  • lsb = 0
  • i2c_size = 2

groups:
['']

fields:

  • [13:0] = ambient_duration_prec_calc

◆ VL53L1_MCU_RANGE_CALC_AMBIENT_DURATION_PRE_CALC_HI

#define VL53L1_MCU_RANGE_CALC_AMBIENT_DURATION_PRE_CALC_HI   0x0438

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_AMBIENT_DURATION_PRE_CALC_LO

#define VL53L1_MCU_RANGE_CALC_AMBIENT_DURATION_PRE_CALC_LO   0x0439

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_AMBIENT_RATE_MCPS

#define VL53L1_MCU_RANGE_CALC_AMBIENT_RATE_MCPS   0x045E

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['']

fields:

  • [15:0] = ambient_rate

◆ VL53L1_MCU_RANGE_CALC_AMBIENT_RATE_MCPS_HI

#define VL53L1_MCU_RANGE_CALC_AMBIENT_RATE_MCPS_HI   0x045E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_AMBIENT_RATE_MCPS_LO

#define VL53L1_MCU_RANGE_CALC_AMBIENT_RATE_MCPS_LO   0x045F

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_AVG_SIGNAL_RATE_MCPS

#define VL53L1_MCU_RANGE_CALC_AVG_SIGNAL_RATE_MCPS   0x045C

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['']

fields:

  • [15:0] = avg_signal_rate

◆ VL53L1_MCU_RANGE_CALC_AVG_SIGNAL_RATE_MCPS_HI

#define VL53L1_MCU_RANGE_CALC_AVG_SIGNAL_RATE_MCPS_HI   0x045C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_AVG_SIGNAL_RATE_MCPS_LO

#define VL53L1_MCU_RANGE_CALC_AVG_SIGNAL_RATE_MCPS_LO   0x045D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_CALC_STATUS

#define VL53L1_MCU_RANGE_CALC_CALC_STATUS   0x0462

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['']

fields:

  • [7:0] = calc_status

◆ VL53L1_MCU_RANGE_CALC_CONFIG

#define VL53L1_MCU_RANGE_CALC_CONFIG   0x0430

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['']

fields:

  • [0] = fw_calc_sigma_delta_sel
  • [2] = fw_calc_phase_output_en
  • [3] = fw_calc_peak_signal_rate_en
  • [4] = fw_calc_ambient_rate_en
  • [5] = fw_calc_total_rate_per_spad_en
  • [6] = fw_calc_snr_avg_signal_rate_en
  • [7] = fw_calc_sigma_en

◆ VL53L1_MCU_RANGE_CALC_DEBUG

#define VL53L1_MCU_RANGE_CALC_DEBUG   0x0463

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['']

fields:

  • [0] = calc_debug_divide_by_zero

◆ VL53L1_MCU_RANGE_CALC_NUM_SPADS

#define VL53L1_MCU_RANGE_CALC_NUM_SPADS   0x0450

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['']

fields:

  • [15:0] = num_spads

◆ VL53L1_MCU_RANGE_CALC_NUM_SPADS_HI

#define VL53L1_MCU_RANGE_CALC_NUM_SPADS_HI   0x0450

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_NUM_SPADS_LO

#define VL53L1_MCU_RANGE_CALC_NUM_SPADS_LO   0x0451

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_OFFSET_CORRECTED_RANGE

#define VL53L1_MCU_RANGE_CALC_OFFSET_CORRECTED_RANGE   0x0432

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['']

fields:

  • [15:0] = offset_corrected_range

◆ VL53L1_MCU_RANGE_CALC_OFFSET_CORRECTED_RANGE_HI

#define VL53L1_MCU_RANGE_CALC_OFFSET_CORRECTED_RANGE_HI   0x0432

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_OFFSET_CORRECTED_RANGE_LO

#define VL53L1_MCU_RANGE_CALC_OFFSET_CORRECTED_RANGE_LO   0x0433

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_PEAK_SIGNAL_RATE_MCPS

#define VL53L1_MCU_RANGE_CALC_PEAK_SIGNAL_RATE_MCPS   0x045A

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['']

fields:

  • [15:0] = peak_signal_rate

◆ VL53L1_MCU_RANGE_CALC_PEAK_SIGNAL_RATE_MCPS_HI

#define VL53L1_MCU_RANGE_CALC_PEAK_SIGNAL_RATE_MCPS_HI   0x045A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_PEAK_SIGNAL_RATE_MCPS_LO

#define VL53L1_MCU_RANGE_CALC_PEAK_SIGNAL_RATE_MCPS_LO   0x045B

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_PEAK_SIGNAL_RATE_XTALK_CORR_MCPS

#define VL53L1_MCU_RANGE_CALC_PEAK_SIGNAL_RATE_XTALK_CORR_MCPS   0x0464

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['']

fields:

  • [15:0] = peak_signal_rate_xtalk_corr

◆ VL53L1_MCU_RANGE_CALC_PEAK_SIGNAL_RATE_XTALK_CORR_MCPS_HI

#define VL53L1_MCU_RANGE_CALC_PEAK_SIGNAL_RATE_XTALK_CORR_MCPS_HI   0x0464

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_PEAK_SIGNAL_RATE_XTALK_CORR_MCPS_LO

#define VL53L1_MCU_RANGE_CALC_PEAK_SIGNAL_RATE_XTALK_CORR_MCPS_LO   0x0465

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_PHASE_OUTPUT

#define VL53L1_MCU_RANGE_CALC_PHASE_OUTPUT   0x0452

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['']

fields:

  • [15:0] = phase_output

◆ VL53L1_MCU_RANGE_CALC_PHASE_OUTPUT_HI

#define VL53L1_MCU_RANGE_CALC_PHASE_OUTPUT_HI   0x0452

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_PHASE_OUTPUT_LO

#define VL53L1_MCU_RANGE_CALC_PHASE_OUTPUT_LO   0x0453

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_RATE_PER_SPAD_MCPS

#define VL53L1_MCU_RANGE_CALC_RATE_PER_SPAD_MCPS   0x0454

type: uint32_t
default: 0x00000000
info:

  • msb = 19
  • lsb = 0
  • i2c_size = 4

groups:
['']

fields:

  • [19:0] = rate_per_spad_mcps

◆ VL53L1_MCU_RANGE_CALC_RATE_PER_SPAD_MCPS_0

#define VL53L1_MCU_RANGE_CALC_RATE_PER_SPAD_MCPS_0   0x0457

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_RATE_PER_SPAD_MCPS_1

#define VL53L1_MCU_RANGE_CALC_RATE_PER_SPAD_MCPS_1   0x0456

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_RATE_PER_SPAD_MCPS_2

#define VL53L1_MCU_RANGE_CALC_RATE_PER_SPAD_MCPS_2   0x0455

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_RATE_PER_SPAD_MCPS_3

#define VL53L1_MCU_RANGE_CALC_RATE_PER_SPAD_MCPS_3   0x0454

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_SPARE_0

#define VL53L1_MCU_RANGE_CALC_SPARE_0   0x0468

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['']

fields:

  • [7:0] = mcu_calc_spare_0

◆ VL53L1_MCU_RANGE_CALC_SPARE_1

#define VL53L1_MCU_RANGE_CALC_SPARE_1   0x0469

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['']

fields:

  • [7:0] = mcu_calc_spare_1

◆ VL53L1_MCU_RANGE_CALC_SPARE_2

#define VL53L1_MCU_RANGE_CALC_SPARE_2   0x046A

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['']

fields:

  • [7:0] = mcu_calc_spare_2

◆ VL53L1_MCU_RANGE_CALC_SPARE_3

#define VL53L1_MCU_RANGE_CALC_SPARE_3   0x046B

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['']

fields:

  • [7:0] = mcu_calc_spare_3

◆ VL53L1_MCU_RANGE_CALC_SPARE_4

#define VL53L1_MCU_RANGE_CALC_SPARE_4   0x0434

type: uint32_t
default: 0x00000000
info:

  • msb = 16
  • lsb = 0
  • i2c_size = 4

groups:
['']

fields:

  • [16:0] = mcu_calc_spare_4

◆ VL53L1_MCU_RANGE_CALC_SPARE_4_0

#define VL53L1_MCU_RANGE_CALC_SPARE_4_0   0x0437

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_SPARE_4_1

#define VL53L1_MCU_RANGE_CALC_SPARE_4_1   0x0436

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_SPARE_4_2

#define VL53L1_MCU_RANGE_CALC_SPARE_4_2   0x0435

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_SPARE_4_3

#define VL53L1_MCU_RANGE_CALC_SPARE_4_3   0x0434

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_SPARE_5

#define VL53L1_MCU_RANGE_CALC_SPARE_5   0x043D

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['']

fields:

  • [7:0] = mcu_calc_spare_5

◆ VL53L1_MCU_RANGE_CALC_SPARE_6

#define VL53L1_MCU_RANGE_CALC_SPARE_6   0x044C

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['']

fields:

  • [15:0] = mcu_calc_spare_6

◆ VL53L1_MCU_RANGE_CALC_SPARE_6_HI

#define VL53L1_MCU_RANGE_CALC_SPARE_6_HI   0x044C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_SPARE_6_LO

#define VL53L1_MCU_RANGE_CALC_SPARE_6_LO   0x044D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_SPARE_7

#define VL53L1_MCU_RANGE_CALC_SPARE_7   0x0458

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['']

fields:

  • [7:0] = mcu_calc_spare_7

◆ VL53L1_MCU_RANGE_CALC_SPARE_8

#define VL53L1_MCU_RANGE_CALC_SPARE_8   0x0459

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['']

fields:

  • [7:0] = mcu_calc_spare_8

◆ VL53L1_MCU_RANGE_CALC_XTALK

#define VL53L1_MCU_RANGE_CALC_XTALK   0x0460

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['']

fields:

  • [15:0] = crosstalk (fixed point 9.7)

◆ VL53L1_MCU_RANGE_CALC_XTALK_HI

#define VL53L1_MCU_RANGE_CALC_XTALK_HI   0x0460

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_RANGE_CALC_XTALK_LO

#define VL53L1_MCU_RANGE_CALC_XTALK_LO   0x0461

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_TO_HOST_BANK_WR_ACCESS_EN

#define VL53L1_MCU_TO_HOST_BANK_WR_ACCESS_EN   0x0100

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'host_bank_ctrl']

fields:

  • [0] = mcu_to_host_bank_wr_en

◆ VL53L1_MCU_UTIL_DIVIDER_DIVIDEND

#define VL53L1_MCU_UTIL_DIVIDER_DIVIDEND   0x0414

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_DIVIDER_DIVIDEND_0

#define VL53L1_MCU_UTIL_DIVIDER_DIVIDEND_0   0x0417

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_DIVIDER_DIVIDEND_1

#define VL53L1_MCU_UTIL_DIVIDER_DIVIDEND_1   0x0416

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_DIVIDER_DIVIDEND_2

#define VL53L1_MCU_UTIL_DIVIDER_DIVIDEND_2   0x0415

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_DIVIDER_DIVIDEND_3

#define VL53L1_MCU_UTIL_DIVIDER_DIVIDEND_3   0x0414

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_DIVIDER_DIVISOR

#define VL53L1_MCU_UTIL_DIVIDER_DIVISOR   0x0418

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_DIVIDER_DIVISOR_0

#define VL53L1_MCU_UTIL_DIVIDER_DIVISOR_0   0x041B

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_DIVIDER_DIVISOR_1

#define VL53L1_MCU_UTIL_DIVIDER_DIVISOR_1   0x041A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_DIVIDER_DIVISOR_2

#define VL53L1_MCU_UTIL_DIVIDER_DIVISOR_2   0x0419

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_DIVIDER_DIVISOR_3

#define VL53L1_MCU_UTIL_DIVIDER_DIVISOR_3   0x0418

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_DIVIDER_QUOTIENT

#define VL53L1_MCU_UTIL_DIVIDER_QUOTIENT   0x041C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_DIVIDER_QUOTIENT_0

#define VL53L1_MCU_UTIL_DIVIDER_QUOTIENT_0   0x041F

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_DIVIDER_QUOTIENT_1

#define VL53L1_MCU_UTIL_DIVIDER_QUOTIENT_1   0x041E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_DIVIDER_QUOTIENT_2

#define VL53L1_MCU_UTIL_DIVIDER_QUOTIENT_2   0x041D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_DIVIDER_QUOTIENT_3

#define VL53L1_MCU_UTIL_DIVIDER_QUOTIENT_3   0x041C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_DIVIDER_START

#define VL53L1_MCU_UTIL_DIVIDER_START   0x0412

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_DIVIDER_STATUS

#define VL53L1_MCU_UTIL_DIVIDER_STATUS   0x0413

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLICAND

#define VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLICAND   0x0400

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLICAND_0

#define VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLICAND_0   0x0403

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLICAND_1

#define VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLICAND_1   0x0402

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLICAND_2

#define VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLICAND_2   0x0401

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLICAND_3

#define VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLICAND_3   0x0400

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLIER

#define VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLIER   0x0404

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLIER_0

#define VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLIER_0   0x0407

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLIER_1

#define VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLIER_1   0x0406

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLIER_2

#define VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLIER_2   0x0405

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLIER_3

#define VL53L1_MCU_UTIL_MULTIPLIER_MULTIPLIER_3   0x0404

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_HI

#define VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_HI   0x0408

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_HI_0

#define VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_HI_0   0x040B

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_HI_1

#define VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_HI_1   0x040A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_HI_2

#define VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_HI_2   0x0409

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_HI_3

#define VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_HI_3   0x0408

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_LO

#define VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_LO   0x040C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_LO_0

#define VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_LO_0   0x040F

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_LO_1

#define VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_LO_1   0x040E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_LO_2

#define VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_LO_2   0x040D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_LO_3

#define VL53L1_MCU_UTIL_MULTIPLIER_PRODUCT_LO_3   0x040C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_MULTIPLIER_START

#define VL53L1_MCU_UTIL_MULTIPLIER_START   0x0410

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MCU_UTIL_MULTIPLIER_STATUS

#define VL53L1_MCU_UTIL_MULTIPLIER_STATUS   0x0411

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MM_CONFIG_INNER_OFFSET_MM

#define VL53L1_MM_CONFIG_INNER_OFFSET_MM   0x0020

type: int16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['customer_nvm_managed', 'mm_config']

fields:

  • [15:0] = mm_config_inner_offset_mm

◆ VL53L1_MM_CONFIG_INNER_OFFSET_MM_HI

#define VL53L1_MM_CONFIG_INNER_OFFSET_MM_HI   0x0020

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MM_CONFIG_INNER_OFFSET_MM_LO

#define VL53L1_MM_CONFIG_INNER_OFFSET_MM_LO   0x0021

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MM_CONFIG_OUTER_OFFSET_MM

#define VL53L1_MM_CONFIG_OUTER_OFFSET_MM   0x0022

type: int16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['customer_nvm_managed', 'mm_config']

fields:

  • [15:0] = mm_config_outer_offset_mm

◆ VL53L1_MM_CONFIG_OUTER_OFFSET_MM_HI

#define VL53L1_MM_CONFIG_OUTER_OFFSET_MM_HI   0x0022

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MM_CONFIG_OUTER_OFFSET_MM_LO

#define VL53L1_MM_CONFIG_OUTER_OFFSET_MM_LO   0x0023

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MM_CONFIG_TIMEOUT_MACROP_A_HI

#define VL53L1_MM_CONFIG_TIMEOUT_MACROP_A_HI   0x005A

type: uint8_t
default: 0x00
info:

  • msb = 3
  • lsb = 0
  • i2c_size = 1

groups:
['timing_config', 'mm_config']

fields:

  • [3:0] = mm_config_config_timeout_macrop_a_hi

◆ VL53L1_MM_CONFIG_TIMEOUT_MACROP_A_LO

#define VL53L1_MM_CONFIG_TIMEOUT_MACROP_A_LO   0x005B

type: uint8_t
default: 0x06
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['timing_config', 'mm_config']

fields:

  • [7:0] = mm_config_config_timeout_macrop_a_lo

◆ VL53L1_MM_CONFIG_TIMEOUT_MACROP_B_HI

#define VL53L1_MM_CONFIG_TIMEOUT_MACROP_B_HI   0x005C

type: uint8_t
default: 0x00
info:

  • msb = 3
  • lsb = 0
  • i2c_size = 1

groups:
['timing_config', 'mm_config']

fields:

  • [3:0] = mm_config_config_timeout_macrop_b_hi

◆ VL53L1_MM_CONFIG_TIMEOUT_MACROP_B_LO

#define VL53L1_MM_CONFIG_TIMEOUT_MACROP_B_LO   0x005D

type: uint8_t
default: 0x06
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['timing_config', 'mm_config']

fields:

  • [7:0] = mm_config_config_timeout_macrop_b_lo

◆ VL53L1_MM_RESULT_INNER_INTERSECTION_RATE

#define VL53L1_MM_RESULT_INNER_INTERSECTION_RATE   0x0F92

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['patch_results', 'mm_results']

fields:

  • [15:0] = mm_result_inner_intersection_rate

◆ VL53L1_MM_RESULT_INNER_INTERSECTION_RATE_HI

#define VL53L1_MM_RESULT_INNER_INTERSECTION_RATE_HI   0x0F92

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MM_RESULT_INNER_INTERSECTION_RATE_LO

#define VL53L1_MM_RESULT_INNER_INTERSECTION_RATE_LO   0x0F93

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MM_RESULT_OUTER_COMPLEMENT_RATE

#define VL53L1_MM_RESULT_OUTER_COMPLEMENT_RATE   0x0F94

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['patch_results', 'mm_results']

fields:

  • [15:0] = mm_result_outer_complement_rate

◆ VL53L1_MM_RESULT_OUTER_COMPLEMENT_RATE_HI

#define VL53L1_MM_RESULT_OUTER_COMPLEMENT_RATE_HI   0x0F94

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MM_RESULT_OUTER_COMPLEMENT_RATE_LO

#define VL53L1_MM_RESULT_OUTER_COMPLEMENT_RATE_LO   0x0F95

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MM_RESULT_TOTAL_OFFSET

#define VL53L1_MM_RESULT_TOTAL_OFFSET   0x0F96

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['patch_results', 'mm_results']

fields:

  • [15:0] = mm_result_total_offset

◆ VL53L1_MM_RESULT_TOTAL_OFFSET_HI

#define VL53L1_MM_RESULT_TOTAL_OFFSET_HI   0x0F96

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_MM_RESULT_TOTAL_OFFSET_LO

#define VL53L1_MM_RESULT_TOTAL_OFFSET_LO   0x0F97

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_NVM_BIST_COMPLETE

#define VL53L1_NVM_BIST_COMPLETE   0x010C

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'nvm_bist_status']

fields:

  • [0] = nvm_bist_complete

◆ VL53L1_NVM_BIST_CTRL

#define VL53L1_NVM_BIST_CTRL   0x0029

type: uint8_t
default: 0x00
info:

  • msb = 4
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'nvm_bist_config']

fields:

  • [2:0] = nvm_bist_cmd
  • [4] = nvm_bist_ctrl

◆ VL53L1_NVM_BIST_NUM_NVM_WORDS

#define VL53L1_NVM_BIST_NUM_NVM_WORDS   0x002A

type: uint8_t
default: 0x00
info:

  • msb = 6
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'nvm_bist_config']

fields:

  • [6:0] = nvm_bist_num_nvm_words

◆ VL53L1_NVM_BIST_START_ADDRESS

#define VL53L1_NVM_BIST_START_ADDRESS   0x002B

type: uint8_t
default: 0x00
info:

  • msb = 6
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'nvm_bist_config']

fields:

  • [6:0] = nvm_bist_start_address

◆ VL53L1_NVM_BIST_STATUS

#define VL53L1_NVM_BIST_STATUS   0x010D

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'nvm_bist_status']

fields:

  • [0] = nvm_bist_status

◆ VL53L1_OSC_MEASURED_FAST_OSC_FREQUENCY

#define VL53L1_OSC_MEASURED_FAST_OSC_FREQUENCY   0x0006

type: uint16_t
default: OSC_FREQUENCY
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['static_nvm_managed', 'analog_config']

fields:

  • [15:0] = osc_frequency (fixed point 4.12)

◆ VL53L1_OSC_MEASURED_FAST_OSC_FREQUENCY_HI

#define VL53L1_OSC_MEASURED_FAST_OSC_FREQUENCY_HI   0x0006

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_OSC_MEASURED_FAST_OSC_FREQUENCY_LO

#define VL53L1_OSC_MEASURED_FAST_OSC_FREQUENCY_LO   0x0007

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PAD_I2C_HV_CONFIG

#define VL53L1_PAD_I2C_HV_CONFIG   0x002D

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'gpio_config']

fields:

  • [0] = pad_scl_sda_vmodeint_hv
  • [1] = i2c_pad_test_hv
  • [2] = pad_scl_fpen_hv
  • [4:3] = pad_scl_progdel_hv
  • [5] = pad_sda_fpen_hv
  • [7:6] = pad_sda_progdel_hv

◆ VL53L1_PAD_I2C_HV_EXTSUP_CONFIG

#define VL53L1_PAD_I2C_HV_EXTSUP_CONFIG   0x002E

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'gpio_config']

fields:

  • [0] = pad_scl_sda_extsup_hv

◆ VL53L1_PAD_I2C_LV_CONFIG

#define VL53L1_PAD_I2C_LV_CONFIG   0x04D0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PAD_STARTUP_MODE_VALUE_CTRL

#define VL53L1_PAD_STARTUP_MODE_VALUE_CTRL   0x0103

type: uint8_t
default: 0x30
info:

  • msb = 5
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'pad_config']

fields:

  • [0] = pad_atest1_val
  • [1] = pad_atest2_val
  • [4] = pad_atest1_dig_enable
  • [5] = pad_atest2_dig_enable

◆ VL53L1_PAD_STARTUP_MODE_VALUE_RO

#define VL53L1_PAD_STARTUP_MODE_VALUE_RO   0x0102

type: uint8_t
default: 0x00
info:

  • msb = 1
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'pad_config']

fields:

  • [0] = pad_atest1_val_ro
  • [1] = pad_atest2_val_ro

◆ VL53L1_PAD_STARTUP_MODE_VALUE_RO_GO1

#define VL53L1_PAD_STARTUP_MODE_VALUE_RO_GO1   0x04D4

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['']

fields:

  • [0] = pad_spi_csn_val_ro

◆ VL53L1_PATCH_ADDRESS_0

#define VL53L1_PATCH_ADDRESS_0   0x0496

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_0_HI

#define VL53L1_PATCH_ADDRESS_0_HI   0x0496

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_0_LO

#define VL53L1_PATCH_ADDRESS_0_LO   0x0497

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_1

#define VL53L1_PATCH_ADDRESS_1   0x0498

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_10

#define VL53L1_PATCH_ADDRESS_10   0x04AA

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_10_HI

#define VL53L1_PATCH_ADDRESS_10_HI   0x04AA

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_10_LO

#define VL53L1_PATCH_ADDRESS_10_LO   0x04AB

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_11

#define VL53L1_PATCH_ADDRESS_11   0x04AC

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_11_HI

#define VL53L1_PATCH_ADDRESS_11_HI   0x04AC

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_11_LO

#define VL53L1_PATCH_ADDRESS_11_LO   0x04AD

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_12

#define VL53L1_PATCH_ADDRESS_12   0x04AE

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_12_HI

#define VL53L1_PATCH_ADDRESS_12_HI   0x04AE

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_12_LO

#define VL53L1_PATCH_ADDRESS_12_LO   0x04AF

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_13

#define VL53L1_PATCH_ADDRESS_13   0x04B0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_13_HI

#define VL53L1_PATCH_ADDRESS_13_HI   0x04B0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_13_LO

#define VL53L1_PATCH_ADDRESS_13_LO   0x04B1

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_14

#define VL53L1_PATCH_ADDRESS_14   0x04B2

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_14_HI

#define VL53L1_PATCH_ADDRESS_14_HI   0x04B2

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_14_LO

#define VL53L1_PATCH_ADDRESS_14_LO   0x04B3

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_15

#define VL53L1_PATCH_ADDRESS_15   0x04B4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_15_HI

#define VL53L1_PATCH_ADDRESS_15_HI   0x04B4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_15_LO

#define VL53L1_PATCH_ADDRESS_15_LO   0x04B5

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_1_HI

#define VL53L1_PATCH_ADDRESS_1_HI   0x0498

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_1_LO

#define VL53L1_PATCH_ADDRESS_1_LO   0x0499

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_2

#define VL53L1_PATCH_ADDRESS_2   0x049A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_2_HI

#define VL53L1_PATCH_ADDRESS_2_HI   0x049A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_2_LO

#define VL53L1_PATCH_ADDRESS_2_LO   0x049B

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_3

#define VL53L1_PATCH_ADDRESS_3   0x049C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_3_HI

#define VL53L1_PATCH_ADDRESS_3_HI   0x049C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_3_LO

#define VL53L1_PATCH_ADDRESS_3_LO   0x049D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_4

#define VL53L1_PATCH_ADDRESS_4   0x049E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_4_HI

#define VL53L1_PATCH_ADDRESS_4_HI   0x049E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_4_LO

#define VL53L1_PATCH_ADDRESS_4_LO   0x049F

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_5

#define VL53L1_PATCH_ADDRESS_5   0x04A0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_5_HI

#define VL53L1_PATCH_ADDRESS_5_HI   0x04A0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_5_LO

#define VL53L1_PATCH_ADDRESS_5_LO   0x04A1

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_6

#define VL53L1_PATCH_ADDRESS_6   0x04A2

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_6_HI

#define VL53L1_PATCH_ADDRESS_6_HI   0x04A2

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_6_LO

#define VL53L1_PATCH_ADDRESS_6_LO   0x04A3

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_7

#define VL53L1_PATCH_ADDRESS_7   0x04A4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_7_HI

#define VL53L1_PATCH_ADDRESS_7_HI   0x04A4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_7_LO

#define VL53L1_PATCH_ADDRESS_7_LO   0x04A5

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_8

#define VL53L1_PATCH_ADDRESS_8   0x04A6

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_8_HI

#define VL53L1_PATCH_ADDRESS_8_HI   0x04A6

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_8_LO

#define VL53L1_PATCH_ADDRESS_8_LO   0x04A7

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_9

#define VL53L1_PATCH_ADDRESS_9   0x04A8

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_9_HI

#define VL53L1_PATCH_ADDRESS_9_HI   0x04A8

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_ADDRESS_9_LO

#define VL53L1_PATCH_ADDRESS_9_LO   0x04A9

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_CTRL

#define VL53L1_PATCH_CTRL   0x0470

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_DATA_ENABLES

#define VL53L1_PATCH_DATA_ENABLES   0x0474

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_DATA_ENABLES_HI

#define VL53L1_PATCH_DATA_ENABLES_HI   0x0474

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_DATA_ENABLES_LO

#define VL53L1_PATCH_DATA_ENABLES_LO   0x0475

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_JMP_ENABLES

#define VL53L1_PATCH_JMP_ENABLES   0x0472

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_JMP_ENABLES_HI

#define VL53L1_PATCH_JMP_ENABLES_HI   0x0472

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_JMP_ENABLES_LO

#define VL53L1_PATCH_JMP_ENABLES_LO   0x0473

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_0

#define VL53L1_PATCH_OFFSET_0   0x0476

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_0_HI

#define VL53L1_PATCH_OFFSET_0_HI   0x0476

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_0_LO

#define VL53L1_PATCH_OFFSET_0_LO   0x0477

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_1

#define VL53L1_PATCH_OFFSET_1   0x0478

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_10

#define VL53L1_PATCH_OFFSET_10   0x048A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_10_HI

#define VL53L1_PATCH_OFFSET_10_HI   0x048A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_10_LO

#define VL53L1_PATCH_OFFSET_10_LO   0x048B

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_11

#define VL53L1_PATCH_OFFSET_11   0x048C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_11_HI

#define VL53L1_PATCH_OFFSET_11_HI   0x048C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_11_LO

#define VL53L1_PATCH_OFFSET_11_LO   0x048D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_12

#define VL53L1_PATCH_OFFSET_12   0x048E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_12_HI

#define VL53L1_PATCH_OFFSET_12_HI   0x048E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_12_LO

#define VL53L1_PATCH_OFFSET_12_LO   0x048F

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_13

#define VL53L1_PATCH_OFFSET_13   0x0490

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_13_HI

#define VL53L1_PATCH_OFFSET_13_HI   0x0490

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_13_LO

#define VL53L1_PATCH_OFFSET_13_LO   0x0491

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_14

#define VL53L1_PATCH_OFFSET_14   0x0492

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_14_HI

#define VL53L1_PATCH_OFFSET_14_HI   0x0492

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_14_LO

#define VL53L1_PATCH_OFFSET_14_LO   0x0493

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_15

#define VL53L1_PATCH_OFFSET_15   0x0494

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_15_HI

#define VL53L1_PATCH_OFFSET_15_HI   0x0494

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_15_LO

#define VL53L1_PATCH_OFFSET_15_LO   0x0495

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_1_HI

#define VL53L1_PATCH_OFFSET_1_HI   0x0478

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_1_LO

#define VL53L1_PATCH_OFFSET_1_LO   0x0479

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_2

#define VL53L1_PATCH_OFFSET_2   0x047A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_2_HI

#define VL53L1_PATCH_OFFSET_2_HI   0x047A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_2_LO

#define VL53L1_PATCH_OFFSET_2_LO   0x047B

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_3

#define VL53L1_PATCH_OFFSET_3   0x047C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_3_HI

#define VL53L1_PATCH_OFFSET_3_HI   0x047C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_3_LO

#define VL53L1_PATCH_OFFSET_3_LO   0x047D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_4

#define VL53L1_PATCH_OFFSET_4   0x047E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_4_HI

#define VL53L1_PATCH_OFFSET_4_HI   0x047E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_4_LO

#define VL53L1_PATCH_OFFSET_4_LO   0x047F

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_5

#define VL53L1_PATCH_OFFSET_5   0x0480

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_5_HI

#define VL53L1_PATCH_OFFSET_5_HI   0x0480

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_5_LO

#define VL53L1_PATCH_OFFSET_5_LO   0x0481

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_6

#define VL53L1_PATCH_OFFSET_6   0x0482

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_6_HI

#define VL53L1_PATCH_OFFSET_6_HI   0x0482

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_6_LO

#define VL53L1_PATCH_OFFSET_6_LO   0x0483

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_7

#define VL53L1_PATCH_OFFSET_7   0x0484

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_7_HI

#define VL53L1_PATCH_OFFSET_7_HI   0x0484

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_7_LO

#define VL53L1_PATCH_OFFSET_7_LO   0x0485

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_8

#define VL53L1_PATCH_OFFSET_8   0x0486

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_8_HI

#define VL53L1_PATCH_OFFSET_8_HI   0x0486

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_8_LO

#define VL53L1_PATCH_OFFSET_8_LO   0x0487

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_9

#define VL53L1_PATCH_OFFSET_9   0x0488

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_9_HI

#define VL53L1_PATCH_OFFSET_9_HI   0x0488

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PATCH_OFFSET_9_LO

#define VL53L1_PATCH_OFFSET_9_LO   0x0489

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PHASECAL_CONFIG_OVERRIDE

#define VL53L1_PHASECAL_CONFIG_OVERRIDE   0x004D

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['general_config', 'phasecal_config']

fields:

  • [0] = phasecal_config_override

◆ VL53L1_PHASECAL_CONFIG_TARGET

#define VL53L1_PHASECAL_CONFIG_TARGET   0x004C

type: uint8_t
default: 0x21
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['general_config', 'phasecal_config']

fields:

  • [7:0] = algo_phasecal_lim

◆ VL53L1_PHASECAL_CONFIG_TIMEOUT_MACROP

#define VL53L1_PHASECAL_CONFIG_TIMEOUT_MACROP   0x004B

type: uint8_t
default: 0x04
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['general_config', 'phasecal_config']

fields:

  • [7:0] = phasecal_config_timeout_macrop

◆ VL53L1_PHASECAL_RESULT_PHASE_OUTPUT_REF

#define VL53L1_PHASECAL_RESULT_PHASE_OUTPUT_REF   0x0F88

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['patch_results', 'phasecal_results']

fields:

  • [15:0] = phasecal_result_normalised_phase_ref

◆ VL53L1_PHASECAL_RESULT_PHASE_OUTPUT_REF_HI

#define VL53L1_PHASECAL_RESULT_PHASE_OUTPUT_REF_HI   0x0F88

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PHASECAL_RESULT_PHASE_OUTPUT_REF_LO

#define VL53L1_PHASECAL_RESULT_PHASE_OUTPUT_REF_LO   0x0F89

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PHASECAL_RESULT_REFERENCE_PHASE

#define VL53L1_PHASECAL_RESULT_REFERENCE_PHASE   0x00D6

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['debug_results', 'phasecal_results']

fields:

  • [15:0] = result_phasecal_reference_phase (fixed point 5.11)

◆ VL53L1_PHASECAL_RESULT_REFERENCE_PHASE_HI

#define VL53L1_PHASECAL_RESULT_REFERENCE_PHASE_HI   0x00D6

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PHASECAL_RESULT_REFERENCE_PHASE_LO

#define VL53L1_PHASECAL_RESULT_REFERENCE_PHASE_LO   0x00D7

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PHASECAL_RESULT_VCSEL_START

#define VL53L1_PHASECAL_RESULT_VCSEL_START   0x00D8

type: uint8_t
default: 0x00
info:

  • msb = 6
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'phasecal_results']

fields:

  • [6:0] = result_phasecal_vcsel_start

◆ VL53L1_PLL_PERIOD_US

#define VL53L1_PLL_PERIOD_US   0x0104

type: uint32_t
default: 0x00000000
info:

  • msb = 17
  • lsb = 0
  • i2c_size = 4

groups:
['debug_results', 'pll_config']

fields:

  • [17:0] = pll_period_us (fixed point 0.24)

◆ VL53L1_PLL_PERIOD_US_0

#define VL53L1_PLL_PERIOD_US_0   0x0107

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PLL_PERIOD_US_1

#define VL53L1_PLL_PERIOD_US_1   0x0106

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PLL_PERIOD_US_2

#define VL53L1_PLL_PERIOD_US_2   0x0105

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PLL_PERIOD_US_3

#define VL53L1_PLL_PERIOD_US_3   0x0104

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_POWER_MANAGEMENT_GO1_POWER_FORCE

#define VL53L1_POWER_MANAGEMENT_GO1_POWER_FORCE   0x0083

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['system_control', 'pwrman_ctrl']

fields:

  • [0] = go1_dig_powerforce

◆ VL53L1_POWER_MANAGEMENT_GO1_RESET_STATUS

#define VL53L1_POWER_MANAGEMENT_GO1_RESET_STATUS   0x0101

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'power_man_status']

fields:

  • [0] = go1_status

◆ VL53L1_PREV_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0

#define VL53L1_PREV_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0   0x0ED8

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['prev_shadow_system_results', 'results']

fields:

  • [15:0] = prev_shadow_result_ambient_count_rate_mcps_sd0 (fixed point 9.7)

◆ VL53L1_PREV_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0_HI

#define VL53L1_PREV_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0_HI   0x0ED8

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0_LO

#define VL53L1_PREV_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0_LO   0x0ED9

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1

#define VL53L1_PREV_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1   0x0EEC

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['prev_shadow_system_results', 'results']

fields:

  • [15:0] = prev_shadow_result_ambient_count_rate_mcps_sd1 (fixed point 9.7)

◆ VL53L1_PREV_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1_HI

#define VL53L1_PREV_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1_HI   0x0EEC

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1_LO

#define VL53L1_PREV_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1_LO   0x0EED

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0

#define VL53L1_PREV_SHADOW_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0   0x0EE6

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['prev_shadow_system_results', 'results']

fields:

  • [15:0] = prev_shadow_result_avg_signal_count_rate_mcps_sd0 (fixed point 9.7)

◆ VL53L1_PREV_SHADOW_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI

#define VL53L1_PREV_SHADOW_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI   0x0EE6

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO

#define VL53L1_PREV_SHADOW_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO   0x0EE7

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0

#define VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0   0x0EFC

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['prev_shadow_core_results', 'ranging_core_results']

fields:

  • [31:0] = prev_shadow_result_core_ambient_window_events_sd0

◆ VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_0

#define VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_0   0x0EFF

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_1

#define VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_1   0x0EFE

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_2

#define VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_2   0x0EFD

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_3

#define VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_3   0x0EFC

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1

#define VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1   0x0F0C

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['prev_shadow_core_results', 'ranging_core_results']

fields:

  • [31:0] = prev_shadow_result_core_ambient_window_events_sd1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_0

#define VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_0   0x0F0F

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_1

#define VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_1   0x0F0E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_2

#define VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_2   0x0F0D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_3

#define VL53L1_PREV_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_3   0x0F0C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0

#define VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0   0x0F00

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['prev_shadow_core_results', 'ranging_core_results']

fields:

  • [31:0] = prev_shadow_result_core_ranging_total_events_sd0

◆ VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_0

#define VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_0   0x0F03

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_1

#define VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_1   0x0F02

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_2

#define VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_2   0x0F01

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_3

#define VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_3   0x0F00

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1

#define VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1   0x0F10

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['prev_shadow_core_results', 'ranging_core_results']

fields:

  • [31:0] = prev_shadow_result_core_ranging_total_events_sd1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_0

#define VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_0   0x0F13

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_1

#define VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_1   0x0F12

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_2

#define VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_2   0x0F11

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_3

#define VL53L1_PREV_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_3   0x0F10

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0

#define VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0   0x0F04

type: int32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['prev_shadow_core_results', 'ranging_core_results']

fields:

  • [31:0] = prev_shadow_result_core_signal_total_events_sd0

◆ VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_0

#define VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_0   0x0F07

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_1

#define VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_1   0x0F06

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_2

#define VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_2   0x0F05

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_3

#define VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_3   0x0F04

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1

#define VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1   0x0F14

type: int32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['prev_shadow_core_results', 'ranging_core_results']

fields:

  • [31:0] = prev_shadow_result_core_signal_total_events_sd1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_0

#define VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_0   0x0F17

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_1

#define VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_1   0x0F16

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_2

#define VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_2   0x0F15

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_3

#define VL53L1_PREV_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_3   0x0F14

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_SPARE_0

#define VL53L1_PREV_SHADOW_RESULT_CORE_SPARE_0   0x0F1C

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['prev_shadow_core_results', 'ranging_core_results']

fields:

  • [7:0] = prev_shadow_result_core_spare_0

◆ VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0

#define VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0   0x0F08

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['prev_shadow_core_results', 'ranging_core_results']

fields:

  • [31:0] = prev_shadow_result_core_total_periods_elapsed_sd0

◆ VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_0

#define VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_0   0x0F0B

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_1

#define VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_1   0x0F0A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_2

#define VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_2   0x0F09

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_3

#define VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_3   0x0F08

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1

#define VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1   0x0F18

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['prev_shadow_core_results', 'ranging_core_results']

fields:

  • [31:0] = prev_shadow_result_core_total_periods_elapsed_sd1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_0

#define VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_0   0x0F1B

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_1

#define VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_1   0x0F1A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_2

#define VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_2   0x0F19

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_3

#define VL53L1_PREV_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_3   0x0F18

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0

#define VL53L1_PREV_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0   0x0ED4

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['prev_shadow_system_results', 'results']

fields:

  • [15:0] = prev_shadow_result_dss_actual_effective_spads_sd0 (fixed point 8.8)

◆ VL53L1_PREV_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI

#define VL53L1_PREV_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI   0x0ED4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO

#define VL53L1_PREV_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO   0x0ED5

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1

#define VL53L1_PREV_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1   0x0EE8

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['prev_shadow_system_results', 'results']

fields:

  • [15:0] = prev_shadow_result_dss_actual_effective_spads_sd1 (fixed point 8.8)

◆ VL53L1_PREV_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI

#define VL53L1_PREV_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI   0x0EE8

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO

#define VL53L1_PREV_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO   0x0EE9

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0

#define VL53L1_PREV_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0   0x0EDE

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['prev_shadow_system_results', 'results']

fields:

  • [15:0] = prev_shadow_result_final_crosstalk_corrected_range_mm_sd0

◆ VL53L1_PREV_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI

#define VL53L1_PREV_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI   0x0EDE

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO

#define VL53L1_PREV_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO   0x0EDF

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1

#define VL53L1_PREV_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1   0x0EF2

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['prev_shadow_system_results', 'results']

fields:

  • [15:0] = prev_shadow_result_final_crosstalk_corrected_range_mm_sd1

◆ VL53L1_PREV_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI

#define VL53L1_PREV_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI   0x0EF2

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO

#define VL53L1_PREV_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO   0x0EF3

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_INTERRUPT_STATUS

#define VL53L1_PREV_SHADOW_RESULT_INTERRUPT_STATUS   0x0ED0

type: uint8_t
default: 0x00
info:

  • msb = 5
  • lsb = 0
  • i2c_size = 1

groups:
['prev_shadow_system_results', 'results']

fields:

  • [2:0] = prev_shadow_int_status
  • [4:3] = prev_shadow_int_error_status
  • [5] = prev_shadow_gph_id_gpio_status

◆ VL53L1_PREV_SHADOW_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0

#define VL53L1_PREV_SHADOW_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0   0x0EE2

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['prev_shadow_system_results', 'results']

fields:

  • [15:0] = prev_shadow_result_mm_inner_actual_effective_spads_sd0 (fixed point 8.8)

◆ VL53L1_PREV_SHADOW_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI

#define VL53L1_PREV_SHADOW_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI   0x0EE2

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO

#define VL53L1_PREV_SHADOW_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO   0x0EE3

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0

#define VL53L1_PREV_SHADOW_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0   0x0EE4

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['prev_shadow_system_results', 'results']

fields:

  • [15:0] = prev_shadow_result_mm_outer_actual_effective_spads_sd0 (fixed point 8.8)

◆ VL53L1_PREV_SHADOW_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI

#define VL53L1_PREV_SHADOW_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI   0x0EE4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO

#define VL53L1_PREV_SHADOW_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO   0x0EE5

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0

#define VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0   0x0EE0

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['prev_shadow_system_results', 'results']

fields:

  • [15:0] = prev_shadow_result_peak_signal_count_rate_crosstalk_corrected_mcps_sd0 (fixed point 9.7)

◆ VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI

#define VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI   0x0EE0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO

#define VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO   0x0EE1

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0

#define VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0   0x0ED6

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['prev_shadow_system_results', 'results']

fields:

  • [15:0] = prev_shadow_result_peak_signal_count_rate_mcps_sd0 (fixed point 9.7)

◆ VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI

#define VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI   0x0ED6

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO

#define VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO   0x0ED7

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1

#define VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1   0x0EEA

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['prev_shadow_system_results', 'results']

fields:

  • [15:0] = prev_shadow_result_peak_signal_count_rate_mcps_sd1 (fixed point 9.7)

◆ VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI

#define VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI   0x0EEA

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO

#define VL53L1_PREV_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO   0x0EEB

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_PHASE_SD0

#define VL53L1_PREV_SHADOW_RESULT_PHASE_SD0   0x0EDC

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['prev_shadow_system_results', 'results']

fields:

  • [15:0] = prev_shadow_result_phase_sd0 (fixed point 5.11)

◆ VL53L1_PREV_SHADOW_RESULT_PHASE_SD0_HI

#define VL53L1_PREV_SHADOW_RESULT_PHASE_SD0_HI   0x0EDC

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_PHASE_SD0_LO

#define VL53L1_PREV_SHADOW_RESULT_PHASE_SD0_LO   0x0EDD

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_PHASE_SD1

#define VL53L1_PREV_SHADOW_RESULT_PHASE_SD1   0x0EF0

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['prev_shadow_system_results', 'results']

fields:

  • [15:0] = prev_shadow_result_phase_sd1 (fixed point 5.11)

◆ VL53L1_PREV_SHADOW_RESULT_PHASE_SD1_HI

#define VL53L1_PREV_SHADOW_RESULT_PHASE_SD1_HI   0x0EF0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_PHASE_SD1_LO

#define VL53L1_PREV_SHADOW_RESULT_PHASE_SD1_LO   0x0EF1

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_RANGE_STATUS

#define VL53L1_PREV_SHADOW_RESULT_RANGE_STATUS   0x0ED1

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['prev_shadow_system_results', 'results']

fields:

  • [4:0] = prev_shadow_range_status
  • [5] = prev_shadow_max_threshold_hit
  • [6] = prev_shadow_min_threshold_hit
  • [7] = prev_shadow_gph_id_range_status

◆ VL53L1_PREV_SHADOW_RESULT_REPORT_STATUS

#define VL53L1_PREV_SHADOW_RESULT_REPORT_STATUS   0x0ED2

type: uint8_t
default: 0x00
info:

  • msb = 3
  • lsb = 0
  • i2c_size = 1

groups:
['prev_shadow_system_results', 'results']

fields:

  • [3:0] = prev_shadow_report_status

◆ VL53L1_PREV_SHADOW_RESULT_SIGMA_SD0

#define VL53L1_PREV_SHADOW_RESULT_SIGMA_SD0   0x0EDA

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['prev_shadow_system_results', 'results']

fields:

  • [15:0] = prev_shadow_result_sigma_sd0 (fixed point 14.2)

◆ VL53L1_PREV_SHADOW_RESULT_SIGMA_SD0_HI

#define VL53L1_PREV_SHADOW_RESULT_SIGMA_SD0_HI   0x0EDA

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_SIGMA_SD0_LO

#define VL53L1_PREV_SHADOW_RESULT_SIGMA_SD0_LO   0x0EDB

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_SIGMA_SD1

#define VL53L1_PREV_SHADOW_RESULT_SIGMA_SD1   0x0EEE

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['prev_shadow_system_results', 'results']

fields:

  • [15:0] = prev_shadow_result_sigma_sd1 (fixed point 14.2)

◆ VL53L1_PREV_SHADOW_RESULT_SIGMA_SD1_HI

#define VL53L1_PREV_SHADOW_RESULT_SIGMA_SD1_HI   0x0EEE

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_SIGMA_SD1_LO

#define VL53L1_PREV_SHADOW_RESULT_SIGMA_SD1_LO   0x0EEF

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_SPARE_0_SD1

#define VL53L1_PREV_SHADOW_RESULT_SPARE_0_SD1   0x0EF4

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['prev_shadow_system_results', 'results']

fields:

  • [15:0] = prev_shadow_result_spare_0_sd1

◆ VL53L1_PREV_SHADOW_RESULT_SPARE_0_SD1_HI

#define VL53L1_PREV_SHADOW_RESULT_SPARE_0_SD1_HI   0x0EF4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_SPARE_0_SD1_LO

#define VL53L1_PREV_SHADOW_RESULT_SPARE_0_SD1_LO   0x0EF5

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_SPARE_1_SD1

#define VL53L1_PREV_SHADOW_RESULT_SPARE_1_SD1   0x0EF6

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['prev_shadow_system_results', 'results']

fields:

  • [15:0] = prev_shadow_result_spare_1_sd1

◆ VL53L1_PREV_SHADOW_RESULT_SPARE_1_SD1_HI

#define VL53L1_PREV_SHADOW_RESULT_SPARE_1_SD1_HI   0x0EF6

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_SPARE_1_SD1_LO

#define VL53L1_PREV_SHADOW_RESULT_SPARE_1_SD1_LO   0x0EF7

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_SPARE_2_SD1

#define VL53L1_PREV_SHADOW_RESULT_SPARE_2_SD1   0x0EF8

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['prev_shadow_system_results', 'results']

fields:

  • [15:0] = prev_shadow_result_spare_2_sd1

◆ VL53L1_PREV_SHADOW_RESULT_SPARE_2_SD1_HI

#define VL53L1_PREV_SHADOW_RESULT_SPARE_2_SD1_HI   0x0EF8

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_SPARE_2_SD1_LO

#define VL53L1_PREV_SHADOW_RESULT_SPARE_2_SD1_LO   0x0EF9

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_SPARE_3_SD1

#define VL53L1_PREV_SHADOW_RESULT_SPARE_3_SD1   0x0EFA

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['prev_shadow_system_results', 'results']

fields:

  • [15:0] = prev_shadow_result_spare_3_sd1

◆ VL53L1_PREV_SHADOW_RESULT_SPARE_3_SD1_HI

#define VL53L1_PREV_SHADOW_RESULT_SPARE_3_SD1_HI   0x0EFA

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_SPARE_3_SD1_LO

#define VL53L1_PREV_SHADOW_RESULT_SPARE_3_SD1_LO   0x0EFB

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PREV_SHADOW_RESULT_STREAM_COUNT

#define VL53L1_PREV_SHADOW_RESULT_STREAM_COUNT   0x0ED3

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['prev_shadow_system_results', 'results']

fields:

  • [7:0] = prev_shadow_result_stream_count

◆ VL53L1_PRIVATE_PATCH_BASE_ADDR_RSLV

#define VL53L1_PRIVATE_PATCH_BASE_ADDR_RSLV   0x0E00

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_PROTECTED_LASER_SAFETY_LOCK_BIT

#define VL53L1_PROTECTED_LASER_SAFETY_LOCK_BIT   0x0119

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'laser_safety']

fields:

  • [0] = laser_safety_lock_bit

◆ VL53L1_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT_MCPS

#define VL53L1_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT_MCPS   0x0066

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['timing_config', 'range_config']

fields:

  • [15:0] = range_config_min_count_rate_rtn_limit_mcps (fixed point 9.7)

◆ VL53L1_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI

#define VL53L1_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI   0x0066

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO

#define VL53L1_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO   0x0067

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGE_CONFIG_SIGMA_THRESH

#define VL53L1_RANGE_CONFIG_SIGMA_THRESH   0x0064

type: uint16_t
default: 0x0080
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['timing_config', 'range_config']

fields:

  • [15:0] = range_config_sigma_thresh (fixed point 14.2)

◆ VL53L1_RANGE_CONFIG_SIGMA_THRESH_HI

#define VL53L1_RANGE_CONFIG_SIGMA_THRESH_HI   0x0064

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGE_CONFIG_SIGMA_THRESH_LO

#define VL53L1_RANGE_CONFIG_SIGMA_THRESH_LO   0x0065

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGE_CONFIG_TIMEOUT_MACROP_A_HI

#define VL53L1_RANGE_CONFIG_TIMEOUT_MACROP_A_HI   0x005E

type: uint8_t
default: 0x01
info:

  • msb = 3
  • lsb = 0
  • i2c_size = 1

groups:
['timing_config', 'range_config']

fields:

  • [3:0] = range_timeout_overall_periods_macrop_a_hi

◆ VL53L1_RANGE_CONFIG_TIMEOUT_MACROP_A_LO

#define VL53L1_RANGE_CONFIG_TIMEOUT_MACROP_A_LO   0x005F

type: uint8_t
default: 0x92
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['timing_config', 'range_config']

fields:

  • [7:0] = range_timeout_overall_periods_macrop_a_lo

◆ VL53L1_RANGE_CONFIG_TIMEOUT_MACROP_B_HI

#define VL53L1_RANGE_CONFIG_TIMEOUT_MACROP_B_HI   0x0061

type: uint8_t
default: 0x01
info:

  • msb = 3
  • lsb = 0
  • i2c_size = 1

groups:
['timing_config', 'range_config']

fields:

  • [3:0] = range_timeout_overall_periods_macrop_b_hi

◆ VL53L1_RANGE_CONFIG_TIMEOUT_MACROP_B_LO

#define VL53L1_RANGE_CONFIG_TIMEOUT_MACROP_B_LO   0x0062

type: uint8_t
default: 0x92
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['timing_config', 'range_config']

fields:

  • [7:0] = range_timeout_overall_periods_macrop_b_lo

◆ VL53L1_RANGE_CONFIG_VALID_PHASE_HIGH

#define VL53L1_RANGE_CONFIG_VALID_PHASE_HIGH   0x0069

type: uint8_t
default: 0x80
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['timing_config', 'range_config']

fields:

  • [7:0] = range_config_valid_phase_high (fixed point 5.3)

◆ VL53L1_RANGE_CONFIG_VALID_PHASE_LOW

#define VL53L1_RANGE_CONFIG_VALID_PHASE_LOW   0x0068

type: uint8_t
default: 0x08
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['timing_config', 'range_config']

fields:

  • [7:0] = range_config_valid_phase_low (fixed point 5.3)

◆ VL53L1_RANGE_CONFIG_VCSEL_PERIOD_A

#define VL53L1_RANGE_CONFIG_VCSEL_PERIOD_A   0x0060

type: uint8_t
default: 0x0B
info:

  • msb = 5
  • lsb = 0
  • i2c_size = 1

groups:
['timing_config', 'range_config']

fields:

  • [5:0] = range_config_vcsel_period_a

◆ VL53L1_RANGE_CONFIG_VCSEL_PERIOD_B

#define VL53L1_RANGE_CONFIG_VCSEL_PERIOD_B   0x0063

type: uint8_t
default: 0x09
info:

  • msb = 5
  • lsb = 0
  • i2c_size = 1

groups:
['timing_config', 'range_config']

fields:

  • [5:0] = range_config_vcsel_period_b

◆ VL53L1_RANGE_RESULT_ACCUM_PHASE

#define VL53L1_RANGE_RESULT_ACCUM_PHASE   0x0FA8

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['patch_results', 'range_results']

fields:

  • [31:0] = range_result_accum_phase

◆ VL53L1_RANGE_RESULT_ACCUM_PHASE_0

#define VL53L1_RANGE_RESULT_ACCUM_PHASE_0   0x0FAB

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGE_RESULT_ACCUM_PHASE_1

#define VL53L1_RANGE_RESULT_ACCUM_PHASE_1   0x0FAA

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGE_RESULT_ACCUM_PHASE_2

#define VL53L1_RANGE_RESULT_ACCUM_PHASE_2   0x0FA9

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGE_RESULT_ACCUM_PHASE_3

#define VL53L1_RANGE_RESULT_ACCUM_PHASE_3   0x0FA8

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGE_RESULT_OFFSET_CORRECTED_RANGE

#define VL53L1_RANGE_RESULT_OFFSET_CORRECTED_RANGE   0x0FAC

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['patch_results', 'range_results']

fields:

  • [15:0] = range_result_offset_corrected_range

◆ VL53L1_RANGE_RESULT_OFFSET_CORRECTED_RANGE_HI

#define VL53L1_RANGE_RESULT_OFFSET_CORRECTED_RANGE_HI   0x0FAC

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGE_RESULT_OFFSET_CORRECTED_RANGE_LO

#define VL53L1_RANGE_RESULT_OFFSET_CORRECTED_RANGE_LO   0x0FAD

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_AMBIENT_MISMATCH_LL

#define VL53L1_RANGING_CORE_AMBIENT_MISMATCH_LL   0x099B

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_AMBIENT_MISMATCH_LM

#define VL53L1_RANGING_CORE_AMBIENT_MISMATCH_LM   0x099A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_AMBIENT_MISMATCH_MM

#define VL53L1_RANGING_CORE_AMBIENT_MISMATCH_MM   0x0999

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_AMBIENT_MISMATCH_REF_LL

#define VL53L1_RANGING_CORE_AMBIENT_MISMATCH_REF_LL   0x09AD

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_AMBIENT_MISMATCH_REF_LM

#define VL53L1_RANGING_CORE_AMBIENT_MISMATCH_REF_LM   0x09AC

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_AMBIENT_MISMATCH_REF_MM

#define VL53L1_RANGING_CORE_AMBIENT_MISMATCH_REF_MM   0x09AB

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_AMBIENT_OFFSET_1_LSB

#define VL53L1_RANGING_CORE_AMBIENT_OFFSET_1_LSB   0x0699

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_AMBIENT_OFFSET_1_MSB

#define VL53L1_RANGING_CORE_AMBIENT_OFFSET_1_MSB   0x0698

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_AMBIENT_OFFSET_REF_1_LSB

#define VL53L1_RANGING_CORE_AMBIENT_OFFSET_REF_1_LSB   0x069B

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_AMBIENT_OFFSET_REF_1_MSB

#define VL53L1_RANGING_CORE_AMBIENT_OFFSET_REF_1_MSB   0x069A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_1_LLL

#define VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_1_LLL   0x098D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_1_LLM

#define VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_1_LLM   0x098C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_1_LMM

#define VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_1_LMM   0x098B

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_1_MMM

#define VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_1_MMM   0x098A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_REF_1_LLL

#define VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_REF_1_LLL   0x099F

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_REF_1_LLM

#define VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_REF_1_LLM   0x099E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_REF_1_LMM

#define VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_REF_1_LMM   0x099D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_REF_1_MMM

#define VL53L1_RANGING_CORE_AMBIENT_WINDOW_EVENTS_REF_1_MMM   0x099C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_CALIB_1

#define VL53L1_RANGING_CORE_CALIB_1   0x06C4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_CALIB_2

#define VL53L1_RANGING_CORE_CALIB_2   0x06C5

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_CALIB_2_A0

#define VL53L1_RANGING_CORE_CALIB_2_A0   0x0A0A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_CALIB_3

#define VL53L1_RANGING_CORE_CALIB_3   0x06C6

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_CLK_CTRL1

#define VL53L1_RANGING_CORE_CLK_CTRL1   0x0683

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_CLK_CTRL2

#define VL53L1_RANGING_CORE_CLK_CTRL2   0x0684

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_CPUMP_1

#define VL53L1_RANGING_CORE_CPUMP_1   0x06B6

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_CPUMP_1_A0

#define VL53L1_RANGING_CORE_CPUMP_1_A0   0x0A22

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_CPUMP_2

#define VL53L1_RANGING_CORE_CPUMP_2   0x06B7

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_CPUMP_3

#define VL53L1_RANGING_CORE_CPUMP_3   0x06B8

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_CUSTOM_FE

#define VL53L1_RANGING_CORE_CUSTOM_FE   0x06CD

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_CUSTOM_FE_2

#define VL53L1_RANGING_CORE_CUSTOM_FE_2   0x06CE

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_CUSTOM_FE_2_A0

#define VL53L1_RANGING_CORE_CUSTOM_FE_2_A0   0x0A20

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_DEVICE_ID

#define VL53L1_RANGING_CORE_DEVICE_ID   0x0680

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_FILTER_STRENGTH_1

#define VL53L1_RANGING_CORE_FILTER_STRENGTH_1   0x069C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_FILTER_STRENGTH_REF_1

#define VL53L1_RANGING_CORE_FILTER_STRENGTH_REF_1   0x069D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_FORCE_CONTINUOUS_AMBIENT

#define VL53L1_RANGING_CORE_FORCE_CONTINUOUS_AMBIENT   0x06A9

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_FORCE_DN_IN

#define VL53L1_RANGING_CORE_FORCE_DN_IN   0x06AF

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_FORCE_HW

#define VL53L1_RANGING_CORE_FORCE_HW   0x06A7

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_FORCE_UP_IN

#define VL53L1_RANGING_CORE_FORCE_UP_IN   0x06AE

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_GPIO_CONFIG_A0

#define VL53L1_RANGING_CORE_GPIO_CONFIG_A0   0x0A00

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_GPIO_DIR

#define VL53L1_RANGING_CORE_GPIO_DIR   0x07BE

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_GPIO_OUT_TESTMUX

#define VL53L1_RANGING_CORE_GPIO_OUT_TESTMUX   0x06CC

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_HIGH_LIMIT_1

#define VL53L1_RANGING_CORE_HIGH_LIMIT_1   0x0691

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_HIGH_LIMIT_REF_1

#define VL53L1_RANGING_CORE_HIGH_LIMIT_REF_1   0x0693

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_INITIAL_PHASE_VALUE_1

#define VL53L1_RANGING_CORE_INITIAL_PHASE_VALUE_1   0x06AC

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_INITIAL_PHASE_VALUE_REF_1

#define VL53L1_RANGING_CORE_INITIAL_PHASE_VALUE_REF_1   0x06AD

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_INTR_MANAGER_A0

#define VL53L1_RANGING_CORE_INTR_MANAGER_A0   0x0A02

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_INVERT_HW

#define VL53L1_RANGING_CORE_INVERT_HW   0x06A6

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_INVERT_UP_DN

#define VL53L1_RANGING_CORE_INVERT_UP_DN   0x06B5

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_LASER_CONTINUITY_STATE

#define VL53L1_RANGING_CORE_LASER_CONTINUITY_STATE   0x0981

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_LASER_SAFETY_2

#define VL53L1_RANGING_CORE_LASER_SAFETY_2   0x06D4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_LOW_LIMIT_1

#define VL53L1_RANGING_CORE_LOW_LIMIT_1   0x0690

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_LOW_LIMIT_REF_1

#define VL53L1_RANGING_CORE_LOW_LIMIT_REF_1   0x0692

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_MONITOR_UP_DN

#define VL53L1_RANGING_CORE_MONITOR_UP_DN   0x06B4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_NVM_CTRL_ADDR

#define VL53L1_RANGING_CORE_NVM_CTRL_ADDR   0x0794

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_NVM_CTRL_DATAIN_LLL

#define VL53L1_RANGING_CORE_NVM_CTRL_DATAIN_LLL   0x078F

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_NVM_CTRL_DATAIN_LLM

#define VL53L1_RANGING_CORE_NVM_CTRL_DATAIN_LLM   0x078E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_NVM_CTRL_DATAIN_LMM

#define VL53L1_RANGING_CORE_NVM_CTRL_DATAIN_LMM   0x078D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_NVM_CTRL_DATAIN_MMM

#define VL53L1_RANGING_CORE_NVM_CTRL_DATAIN_MMM   0x078C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_NVM_CTRL_DATAOUT_ECC

#define VL53L1_RANGING_CORE_NVM_CTRL_DATAOUT_ECC   0x0795

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_NVM_CTRL_DATAOUT_LLL

#define VL53L1_RANGING_CORE_NVM_CTRL_DATAOUT_LLL   0x0793

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_NVM_CTRL_DATAOUT_LLM

#define VL53L1_RANGING_CORE_NVM_CTRL_DATAOUT_LLM   0x0792

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_NVM_CTRL_DATAOUT_LMM

#define VL53L1_RANGING_CORE_NVM_CTRL_DATAOUT_LMM   0x0791

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_NVM_CTRL_DATAOUT_MMM

#define VL53L1_RANGING_CORE_NVM_CTRL_DATAOUT_MMM   0x0790

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_NVM_CTRL_HV_FALL_LSB

#define VL53L1_RANGING_CORE_NVM_CTRL_HV_FALL_LSB   0x0789

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_NVM_CTRL_HV_FALL_MSB

#define VL53L1_RANGING_CORE_NVM_CTRL_HV_FALL_MSB   0x0788

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_NVM_CTRL_HV_RISE_LSB

#define VL53L1_RANGING_CORE_NVM_CTRL_HV_RISE_LSB   0x0787

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_NVM_CTRL_HV_RISE_MSB

#define VL53L1_RANGING_CORE_NVM_CTRL_HV_RISE_MSB   0x0786

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_NVM_CTRL_MODE

#define VL53L1_RANGING_CORE_NVM_CTRL_MODE   0x0780

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_NVM_CTRL_PDN

#define VL53L1_RANGING_CORE_NVM_CTRL_PDN   0x0781

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_NVM_CTRL_PROGN

#define VL53L1_RANGING_CORE_NVM_CTRL_PROGN   0x0782

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_NVM_CTRL_PULSE_WIDTH_LSB

#define VL53L1_RANGING_CORE_NVM_CTRL_PULSE_WIDTH_LSB   0x0785

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_NVM_CTRL_PULSE_WIDTH_MSB

#define VL53L1_RANGING_CORE_NVM_CTRL_PULSE_WIDTH_MSB   0x0784

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_NVM_CTRL_READN

#define VL53L1_RANGING_CORE_NVM_CTRL_READN   0x0783

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_NVM_CTRL_TESTREAD

#define VL53L1_RANGING_CORE_NVM_CTRL_TESTREAD   0x078B

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_NVM_CTRL_TST

#define VL53L1_RANGING_CORE_NVM_CTRL_TST   0x078A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_OSC_1

#define VL53L1_RANGING_CORE_OSC_1   0x06B9

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_PLL_1

#define VL53L1_RANGING_CORE_PLL_1   0x06BB

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_PLL_2

#define VL53L1_RANGING_CORE_PLL_2   0x06BC

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_POWER_FSM_TIME_OSC_A0

#define VL53L1_RANGING_CORE_POWER_FSM_TIME_OSC_A0   0x0A06

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_QUANTIFIER_1_LSB

#define VL53L1_RANGING_CORE_QUANTIFIER_1_LSB   0x0695

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_QUANTIFIER_1_MSB

#define VL53L1_RANGING_CORE_QUANTIFIER_1_MSB   0x0694

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_QUANTIFIER_REF_1_LSB

#define VL53L1_RANGING_CORE_QUANTIFIER_REF_1_LSB   0x0697

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_QUANTIFIER_REF_1_MSB

#define VL53L1_RANGING_CORE_QUANTIFIER_REF_1_MSB   0x0696

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RANGE_1_LLL

#define VL53L1_RANGING_CORE_RANGE_1_LLL   0x0985

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RANGE_1_LLM

#define VL53L1_RANGING_CORE_RANGE_1_LLM   0x0984

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RANGE_1_LMM

#define VL53L1_RANGING_CORE_RANGE_1_LMM   0x0983

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RANGE_1_MMM

#define VL53L1_RANGING_CORE_RANGE_1_MMM   0x0982

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RANGE_REF_1_LLL

#define VL53L1_RANGING_CORE_RANGE_REF_1_LLL   0x0989

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RANGE_REF_1_LLM

#define VL53L1_RANGING_CORE_RANGE_REF_1_LLM   0x0988

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RANGE_REF_1_LMM

#define VL53L1_RANGING_CORE_RANGE_REF_1_LMM   0x0987

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RANGE_REF_1_MMM

#define VL53L1_RANGING_CORE_RANGE_REF_1_MMM   0x0986

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_1_LLL

#define VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_1_LLL   0x0991

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_1_LLM

#define VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_1_LLM   0x0990

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_1_LMM

#define VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_1_LMM   0x098F

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_1_MMM

#define VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_1_MMM   0x098E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_REF_1_LLL

#define VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_REF_1_LLL   0x09A3

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_REF_1_LLM

#define VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_REF_1_LLM   0x09A2

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_REF_1_LMM

#define VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_REF_1_LMM   0x09A1

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_REF_1_MMM

#define VL53L1_RANGING_CORE_RANGING_TOTAL_EVENTS_REF_1_MMM   0x09A0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_READOUT_CFG_A0

#define VL53L1_RANGING_CORE_READOUT_CFG_A0   0x0A0D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_REF_EN_START_SELECT

#define VL53L1_RANGING_CORE_REF_EN_START_SELECT   0x0A39

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_REF_SPAD_EN_0_EWOK

#define VL53L1_RANGING_CORE_REF_SPAD_EN_0_EWOK   0x0A33

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_REF_SPAD_EN_1_EWOK

#define VL53L1_RANGING_CORE_REF_SPAD_EN_1_EWOK   0x0A34

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_REF_SPAD_EN_2_EWOK

#define VL53L1_RANGING_CORE_REF_SPAD_EN_2_EWOK   0x0A35

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_REF_SPAD_EN_3_EWOK

#define VL53L1_RANGING_CORE_REF_SPAD_EN_3_EWOK   0x0A36

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_REF_SPAD_EN_4_EWOK

#define VL53L1_RANGING_CORE_REF_SPAD_EN_4_EWOK   0x0A37

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_REF_SPAD_EN_5_EWOK

#define VL53L1_RANGING_CORE_REF_SPAD_EN_5_EWOK   0x0A38

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_REFERENCE_1

#define VL53L1_RANGING_CORE_REFERENCE_1   0x06BD

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_REFERENCE_2_A0

#define VL53L1_RANGING_CORE_REFERENCE_2_A0   0x0A1B

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_REFERENCE_3

#define VL53L1_RANGING_CORE_REFERENCE_3   0x06BF

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_REFERENCE_4

#define VL53L1_RANGING_CORE_REFERENCE_4   0x06C0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_REFERENCE_5

#define VL53L1_RANGING_CORE_REFERENCE_5   0x06C1

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_REGAVDD1V2

#define VL53L1_RANGING_CORE_REGAVDD1V2   0x06C3

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_REGAVDD1V2_A0

#define VL53L1_RANGING_CORE_REGAVDD1V2_A0   0x0A1D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_REGDVDD1V2_ATEST_EWOK

#define VL53L1_RANGING_CORE_REGDVDD1V2_ATEST_EWOK   0x0A41

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RESET_CONTROL_A0

#define VL53L1_RANGING_CORE_RESET_CONTROL_A0   0x0A01

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_0

#define VL53L1_RANGING_CORE_RET_SPAD_EN_0   0x0796

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_1

#define VL53L1_RANGING_CORE_RET_SPAD_EN_1   0x0797

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_10

#define VL53L1_RANGING_CORE_RET_SPAD_EN_10   0x07A0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_11

#define VL53L1_RANGING_CORE_RET_SPAD_EN_11   0x07A1

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_12

#define VL53L1_RANGING_CORE_RET_SPAD_EN_12   0x07A2

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_13

#define VL53L1_RANGING_CORE_RET_SPAD_EN_13   0x07A3

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_14

#define VL53L1_RANGING_CORE_RET_SPAD_EN_14   0x07A4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_15

#define VL53L1_RANGING_CORE_RET_SPAD_EN_15   0x07A5

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_16

#define VL53L1_RANGING_CORE_RET_SPAD_EN_16   0x07A6

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_17

#define VL53L1_RANGING_CORE_RET_SPAD_EN_17   0x07A7

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_18

#define VL53L1_RANGING_CORE_RET_SPAD_EN_18   0x0A25

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_19

#define VL53L1_RANGING_CORE_RET_SPAD_EN_19   0x0A26

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_2

#define VL53L1_RANGING_CORE_RET_SPAD_EN_2   0x0798

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_20

#define VL53L1_RANGING_CORE_RET_SPAD_EN_20   0x0A27

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_21

#define VL53L1_RANGING_CORE_RET_SPAD_EN_21   0x0A28

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_22

#define VL53L1_RANGING_CORE_RET_SPAD_EN_22   0x0A29

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_23

#define VL53L1_RANGING_CORE_RET_SPAD_EN_23   0x0A2A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_24

#define VL53L1_RANGING_CORE_RET_SPAD_EN_24   0x0A2B

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_25

#define VL53L1_RANGING_CORE_RET_SPAD_EN_25   0x0A2C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_26

#define VL53L1_RANGING_CORE_RET_SPAD_EN_26   0x0A2D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_27

#define VL53L1_RANGING_CORE_RET_SPAD_EN_27   0x0A2E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_28

#define VL53L1_RANGING_CORE_RET_SPAD_EN_28   0x0A2F

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_29

#define VL53L1_RANGING_CORE_RET_SPAD_EN_29   0x0A30

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_3

#define VL53L1_RANGING_CORE_RET_SPAD_EN_3   0x0799

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_30

#define VL53L1_RANGING_CORE_RET_SPAD_EN_30   0x0A31

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_31

#define VL53L1_RANGING_CORE_RET_SPAD_EN_31   0x0A32

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_4

#define VL53L1_RANGING_CORE_RET_SPAD_EN_4   0x079A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_5

#define VL53L1_RANGING_CORE_RET_SPAD_EN_5   0x079B

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_6

#define VL53L1_RANGING_CORE_RET_SPAD_EN_6   0x079C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_7

#define VL53L1_RANGING_CORE_RET_SPAD_EN_7   0x079D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_8

#define VL53L1_RANGING_CORE_RET_SPAD_EN_8   0x079E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_RET_SPAD_EN_9

#define VL53L1_RANGING_CORE_RET_SPAD_EN_9   0x079F

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_REVISION_ID

#define VL53L1_RANGING_CORE_REVISION_ID   0x0681

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_SIGNAL_EVENT_LIMIT_1_LSB

#define VL53L1_RANGING_CORE_SIGNAL_EVENT_LIMIT_1_LSB   0x069F

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_SIGNAL_EVENT_LIMIT_1_MSB

#define VL53L1_RANGING_CORE_SIGNAL_EVENT_LIMIT_1_MSB   0x069E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_SIGNAL_EVENT_LIMIT_REF_1_LSB

#define VL53L1_RANGING_CORE_SIGNAL_EVENT_LIMIT_REF_1_LSB   0x06A1

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_SIGNAL_EVENT_LIMIT_REF_1_MSB

#define VL53L1_RANGING_CORE_SIGNAL_EVENT_LIMIT_REF_1_MSB   0x06A0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_1_LLL

#define VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_1_LLL   0x0995

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_1_LLM

#define VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_1_LLM   0x0994

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_1_LMM

#define VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_1_LMM   0x0993

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_1_MMM

#define VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_1_MMM   0x0992

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_REF_1_LLL

#define VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_REF_1_LLL   0x09A7

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_REF_1_LLM

#define VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_REF_1_LLM   0x09A6

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_REF_1_LMM

#define VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_REF_1_LMM   0x09A5

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_REF_1_MMM

#define VL53L1_RANGING_CORE_SIGNAL_TOTAL_EVENTS_REF_1_MMM   0x09A4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_SPAD_DISABLE_CTRL

#define VL53L1_RANGING_CORE_SPAD_DISABLE_CTRL   0x07BB

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_SPAD_EN_SHIFT_OUT_DEBUG

#define VL53L1_RANGING_CORE_SPAD_EN_SHIFT_OUT_DEBUG   0x07BC

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_SPAD_PS

#define VL53L1_RANGING_CORE_SPAD_PS   0x06D2

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_SPAD_READOUT

#define VL53L1_RANGING_CORE_SPAD_READOUT   0x06CF

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_SPAD_READOUT_1

#define VL53L1_RANGING_CORE_SPAD_READOUT_1   0x06D0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_SPAD_READOUT_2

#define VL53L1_RANGING_CORE_SPAD_READOUT_2   0x06D1

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_SPAD_READOUT_A0

#define VL53L1_RANGING_CORE_SPAD_READOUT_A0   0x0A21

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_SPAD_SHIFT_EN

#define VL53L1_RANGING_CORE_SPAD_SHIFT_EN   0x07BA

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_SPARE_REGISTER_A0

#define VL53L1_RANGING_CORE_SPARE_REGISTER_A0   0x0A23

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_SPI_MODE

#define VL53L1_RANGING_CORE_SPI_MODE   0x07BD

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_START_RANGING

#define VL53L1_RANGING_CORE_START_RANGING   0x0687

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_STATIC_DN_VALUE_1

#define VL53L1_RANGING_CORE_STATIC_DN_VALUE_1   0x06B2

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_STATIC_DN_VALUE_REF_1

#define VL53L1_RANGING_CORE_STATIC_DN_VALUE_REF_1   0x06B3

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_STATIC_HW_VALUE

#define VL53L1_RANGING_CORE_STATIC_HW_VALUE   0x06A8

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_STATIC_UP_VALUE_1

#define VL53L1_RANGING_CORE_STATIC_UP_VALUE_1   0x06B0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_STATIC_UP_VALUE_REF_1

#define VL53L1_RANGING_CORE_STATIC_UP_VALUE_REF_1   0x06B1

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_STATUS

#define VL53L1_RANGING_CORE_STATUS   0x0980

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_STATUS_RESET_A0

#define VL53L1_RANGING_CORE_STATUS_RESET_A0   0x0A0C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_STOP_CONDITION_A0

#define VL53L1_RANGING_CORE_STOP_CONDITION_A0   0x0A0B

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_TEST_PHASE_SELECT_TO_FILTER

#define VL53L1_RANGING_CORE_TEST_PHASE_SELECT_TO_FILTER   0x06AA

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_TEST_PHASE_SELECT_TO_TIMING_GEN

#define VL53L1_RANGING_CORE_TEST_PHASE_SELECT_TO_TIMING_GEN   0x06AB

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_TIMEOUT_OVERALL_PERIODS_LSB

#define VL53L1_RANGING_CORE_TIMEOUT_OVERALL_PERIODS_LSB   0x06A5

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_TIMEOUT_OVERALL_PERIODS_MSB

#define VL53L1_RANGING_CORE_TIMEOUT_OVERALL_PERIODS_MSB   0x06A4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_TOTAL_PERIODS_ELAPSED_1_LL

#define VL53L1_RANGING_CORE_TOTAL_PERIODS_ELAPSED_1_LL   0x0998

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_TOTAL_PERIODS_ELAPSED_1_LM

#define VL53L1_RANGING_CORE_TOTAL_PERIODS_ELAPSED_1_LM   0x0997

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_TOTAL_PERIODS_ELAPSED_1_MM

#define VL53L1_RANGING_CORE_TOTAL_PERIODS_ELAPSED_1_MM   0x0996

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_TOTAL_PERIODS_ELAPSED_REF_1_LL

#define VL53L1_RANGING_CORE_TOTAL_PERIODS_ELAPSED_REF_1_LL   0x09AA

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_TOTAL_PERIODS_ELAPSED_REF_1_LM

#define VL53L1_RANGING_CORE_TOTAL_PERIODS_ELAPSED_REF_1_LM   0x09A9

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_TOTAL_PERIODS_ELAPSED_REF_1_MM

#define VL53L1_RANGING_CORE_TOTAL_PERIODS_ELAPSED_REF_1_MM   0x09A8

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_TST_MUX

#define VL53L1_RANGING_CORE_TST_MUX   0x06CB

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_TST_MUX_A0

#define VL53L1_RANGING_CORE_TST_MUX_A0   0x0A1F

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_TST_MUX_SEL1

#define VL53L1_RANGING_CORE_TST_MUX_SEL1   0x06C9

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_TST_MUX_SEL2

#define VL53L1_RANGING_CORE_TST_MUX_SEL2   0x06CA

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_VCSEL_1

#define VL53L1_RANGING_CORE_VCSEL_1   0x0885

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_VCSEL_ATEST_A0

#define VL53L1_RANGING_CORE_VCSEL_ATEST_A0   0x0A07

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_VCSEL_CONT_STAGE5_BYPASS_A0

#define VL53L1_RANGING_CORE_VCSEL_CONT_STAGE5_BYPASS_A0   0x0A24

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_VCSEL_DELAY_A0

#define VL53L1_RANGING_CORE_VCSEL_DELAY_A0   0x0A1A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_VCSEL_PERIOD

#define VL53L1_RANGING_CORE_VCSEL_PERIOD   0x0880

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_VCSEL_PERIOD_CLIPPED_A0

#define VL53L1_RANGING_CORE_VCSEL_PERIOD_CLIPPED_A0   0x0A08

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_VCSEL_START

#define VL53L1_RANGING_CORE_VCSEL_START   0x0881

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_VCSEL_STATUS

#define VL53L1_RANGING_CORE_VCSEL_STATUS   0x088D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_VCSEL_STOP

#define VL53L1_RANGING_CORE_VCSEL_STOP   0x0882

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_VCSEL_STOP_CLIPPED_A0

#define VL53L1_RANGING_CORE_VCSEL_STOP_CLIPPED_A0   0x0A09

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_WINDOW_SETTING_A0

#define VL53L1_RANGING_CORE_WINDOW_SETTING_A0   0x0A0E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_WOI_1

#define VL53L1_RANGING_CORE_WOI_1   0x0685

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RANGING_CORE_WOI_REF_1

#define VL53L1_RANGING_CORE_WOI_REF_1   0x0686

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_REF_SPAD_CHAR_RESULT_NUM_ACTUAL_REF_SPADS

#define VL53L1_REF_SPAD_CHAR_RESULT_NUM_ACTUAL_REF_SPADS   0x00D9

type: uint8_t
default: 0x00
info:

  • msb = 5
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'ref_spad_status']

fields:

  • [5:0] = ref_spad_char_result_num_actual_ref_spads

◆ VL53L1_REF_SPAD_CHAR_RESULT_REF_LOCATION

#define VL53L1_REF_SPAD_CHAR_RESULT_REF_LOCATION   0x00DA

type: uint8_t
default: 0x00
info:

  • msb = 1
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'ref_spad_status']

fields:

  • [1:0] = ref_spad_char_result_ref_location

◆ VL53L1_REF_SPAD_CHAR_TOTAL_RATE_TARGET_MCPS

#define VL53L1_REF_SPAD_CHAR_TOTAL_RATE_TARGET_MCPS   0x001C

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['customer_nvm_managed', 'ref_spad_char']

fields:

  • [15:0] = ref_spad_char_total_rate_target_mcps (fixed point 9.7)

◆ VL53L1_REF_SPAD_CHAR_TOTAL_RATE_TARGET_MCPS_HI

#define VL53L1_REF_SPAD_CHAR_TOTAL_RATE_TARGET_MCPS_HI   0x001C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_REF_SPAD_CHAR_TOTAL_RATE_TARGET_MCPS_LO

#define VL53L1_REF_SPAD_CHAR_TOTAL_RATE_TARGET_MCPS_LO   0x001D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_REF_SPAD_MAN_NUM_REQUESTED_REF_SPADS

#define VL53L1_REF_SPAD_MAN_NUM_REQUESTED_REF_SPADS   0x0014

type: uint8_t
default: 0x2C
info:

  • msb = 5
  • lsb = 0
  • i2c_size = 1

groups:
['customer_nvm_managed', 'ref_spad_config']

fields:

  • [5:0] = ref_spad_man_num_requested_ref_spad

◆ VL53L1_REF_SPAD_MAN_REF_LOCATION

#define VL53L1_REF_SPAD_MAN_REF_LOCATION   0x0015

type: uint8_t
default: 0x00
info:

  • msb = 1
  • lsb = 0
  • i2c_size = 1

groups:
['customer_nvm_managed', 'ref_spad_config']

fields:

  • [1:0] = ref_spad_man_ref_location

◆ VL53L1_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0

#define VL53L1_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0   0x0090

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['system_results', 'results']

fields:

  • [15:0] = result_ambient_count_rate_mcps_sd0 (fixed point 9.7)

◆ VL53L1_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0_HI

#define VL53L1_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0_HI   0x0090

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0_LO

#define VL53L1_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0_LO   0x0091

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1

#define VL53L1_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1   0x00A4

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['system_results', 'results']

fields:

  • [15:0] = result_ambient_count_rate_mcps_sd1 (fixed point 9.7)

◆ VL53L1_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1_HI

#define VL53L1_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1_HI   0x00A4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1_LO

#define VL53L1_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1_LO   0x00A5

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0

#define VL53L1_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0   0x009E

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['system_results', 'results']

fields:

  • [15:0] = result_avg_signal_count_rate_mcps_sd0 (fixed point 9.7)

◆ VL53L1_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI

#define VL53L1_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI   0x009E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO

#define VL53L1_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO   0x009F

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0

#define VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0   0x00B4

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['core_results', 'ranging_core_results']

fields:

  • [31:0] = result_core_ambient_window_events_sd0

◆ VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_0

#define VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_0   0x00B7

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_1

#define VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_1   0x00B6

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_2

#define VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_2   0x00B5

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_3

#define VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_3   0x00B4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1

#define VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1   0x00C4

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['core_results', 'ranging_core_results']

fields:

  • [31:0] = result_core_ambient_window_events_sd1

◆ VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_0

#define VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_0   0x00C7

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_1

#define VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_1   0x00C6

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_2

#define VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_2   0x00C5

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_3

#define VL53L1_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_3   0x00C4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0

#define VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0   0x00B8

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['core_results', 'ranging_core_results']

fields:

  • [31:0] = result_core_ranging_total_events_sd0

◆ VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_0

#define VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_0   0x00BB

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_1

#define VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_1   0x00BA

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_2

#define VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_2   0x00B9

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_3

#define VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_3   0x00B8

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1

#define VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1   0x00C8

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['core_results', 'ranging_core_results']

fields:

  • [31:0] = result_core_ranging_total_events_sd1

◆ VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_0

#define VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_0   0x00CB

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_1

#define VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_1   0x00CA

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_2

#define VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_2   0x00C9

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_3

#define VL53L1_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_3   0x00C8

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0

#define VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0   0x00BC

type: int32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['core_results', 'ranging_core_results']

fields:

  • [31:0] = result_core_signal_total_events_sd0

◆ VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_0

#define VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_0   0x00BF

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_1

#define VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_1   0x00BE

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_2

#define VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_2   0x00BD

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_3

#define VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_3   0x00BC

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1

#define VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1   0x00CC

type: int32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['core_results', 'ranging_core_results']

fields:

  • [31:0] = result_core_signal_total_events_sd1

◆ VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_0

#define VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_0   0x00CF

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_1

#define VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_1   0x00CE

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_2

#define VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_2   0x00CD

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_3

#define VL53L1_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_3   0x00CC

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_SPARE_0

#define VL53L1_RESULT_CORE_SPARE_0   0x00D4

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['core_results', 'ranging_core_results']

fields:

  • [7:0] = result_core_spare_0

◆ VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0

#define VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0   0x00C0

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['core_results', 'ranging_core_results']

fields:

  • [31:0] = result_core_total_periods_elapsed_sd0

◆ VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_0

#define VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_0   0x00C3

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_1

#define VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_1   0x00C2

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_2

#define VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_2   0x00C1

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_3

#define VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_3   0x00C0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1

#define VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1   0x00D0

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['core_results', 'ranging_core_results']

fields:

  • [31:0] = result_core_total_periods_elapsed_sd1

◆ VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_0

#define VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_0   0x00D3

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_1

#define VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_1   0x00D2

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_2

#define VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_2   0x00D1

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_3

#define VL53L1_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_3   0x00D0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_DEBUG_STAGE

#define VL53L1_RESULT_DEBUG_STAGE   0x0F21

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_debug', 'misc_results']

fields:

  • [7:0] = result_debug_stage

◆ VL53L1_RESULT_DEBUG_STATUS

#define VL53L1_RESULT_DEBUG_STATUS   0x0F20

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_debug', 'misc_results']

fields:

  • [7:0] = result_debug_status

◆ VL53L1_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0

#define VL53L1_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0   0x008C

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['system_results', 'results']

fields:

  • [15:0] = result_dss_actual_effective_spads_sd0 (fixed point 8.8)

◆ VL53L1_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI

#define VL53L1_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI   0x008C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO

#define VL53L1_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO   0x008D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1

#define VL53L1_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1   0x00A0

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['system_results', 'results']

fields:

  • [15:0] = result_dss_actual_effective_spads_sd1 (fixed point 8.8)

◆ VL53L1_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI

#define VL53L1_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI   0x00A0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO

#define VL53L1_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO   0x00A1

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0

#define VL53L1_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0   0x0096

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['system_results', 'results']

fields:

  • [15:0] = result_final_crosstalk_corrected_range_mm_sd0

◆ VL53L1_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI

#define VL53L1_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI   0x0096

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO

#define VL53L1_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO   0x0097

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1

#define VL53L1_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1   0x00AA

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['system_results', 'results']

fields:

  • [15:0] = result_final_crosstalk_corrected_range_mm_sd1

◆ VL53L1_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI

#define VL53L1_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI   0x00AA

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO

#define VL53L1_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO   0x00AB

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_INTERRUPT_STATUS

#define VL53L1_RESULT_INTERRUPT_STATUS   0x0088

type: uint8_t
default: 0x00
info:

  • msb = 5
  • lsb = 0
  • i2c_size = 1

groups:
['system_results', 'results']

fields:

  • [2:0] = int_status
  • [4:3] = int_error_status
  • [5] = gph_id_gpio_status

◆ VL53L1_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0

#define VL53L1_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0   0x009A

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['system_results', 'results']

fields:

  • [15:0] = result_mm_inner_actual_effective_spads_sd0 (fixed point 8.8)

◆ VL53L1_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI

#define VL53L1_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI   0x009A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO

#define VL53L1_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO   0x009B

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0

#define VL53L1_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0   0x009C

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['system_results', 'results']

fields:

  • [15:0] = result_mm_outer_actual_effective_spads_sd0 (fixed point 8.8)

◆ VL53L1_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI

#define VL53L1_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI   0x009C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO

#define VL53L1_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO   0x009D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_OSC_CALIBRATE_VAL

#define VL53L1_RESULT_OSC_CALIBRATE_VAL   0x00DE

type: uint16_t
default: 0x0000
info:

  • msb = 9
  • lsb = 0
  • i2c_size = 2

groups:
['debug_results', 'misc_results']

fields:

  • [9:0] = osc_calibrate_val

◆ VL53L1_RESULT_OSC_CALIBRATE_VAL_HI

#define VL53L1_RESULT_OSC_CALIBRATE_VAL_HI   0x00DE

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_OSC_CALIBRATE_VAL_LO

#define VL53L1_RESULT_OSC_CALIBRATE_VAL_LO   0x00DF

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0

#define VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0   0x0098

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['system_results', 'results']

fields:

  • [15:0] = result_peak_signal_count_rate_crosstalk_corrected_mcps_sd0 (fixed point 9.7)

◆ VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI

#define VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI   0x0098

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO

#define VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO   0x0099

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0

#define VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0   0x008E

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['system_results', 'results']

fields:

  • [15:0] = result_peak_signal_count_rate_mcps_sd0 (fixed point 9.7)

◆ VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI

#define VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI   0x008E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO

#define VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO   0x008F

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1

#define VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1   0x00A2

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['system_results', 'results']

fields:

  • [15:0] = result_peak_signal_count_rate_mcps_sd1 (fixed point 9.7)

◆ VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI

#define VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI   0x00A2

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO

#define VL53L1_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO   0x00A3

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_PHASE_SD0

#define VL53L1_RESULT_PHASE_SD0   0x0094

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['system_results', 'results']

fields:

  • [15:0] = result_phase_sd0 (fixed point 5.11)

◆ VL53L1_RESULT_PHASE_SD0_HI

#define VL53L1_RESULT_PHASE_SD0_HI   0x0094

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_PHASE_SD0_LO

#define VL53L1_RESULT_PHASE_SD0_LO   0x0095

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_PHASE_SD1

#define VL53L1_RESULT_PHASE_SD1   0x00A8

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['system_results', 'results']

fields:

  • [15:0] = result_phase_sd1 (fixed point 5.11)

◆ VL53L1_RESULT_PHASE_SD1_HI

#define VL53L1_RESULT_PHASE_SD1_HI   0x00A8

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_PHASE_SD1_LO

#define VL53L1_RESULT_PHASE_SD1_LO   0x00A9

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_RANGE_STATUS

#define VL53L1_RESULT_RANGE_STATUS   0x0089

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['system_results', 'results']

fields:

  • [4:0] = range_status
  • [5] = max_threshold_hit
  • [6] = min_threshold_hit
  • [7] = gph_id_range_status

◆ VL53L1_RESULT_REPORT_STATUS

#define VL53L1_RESULT_REPORT_STATUS   0x008A

type: uint8_t
default: 0x00
info:

  • msb = 3
  • lsb = 0
  • i2c_size = 1

groups:
['system_results', 'results']

fields:

  • [3:0] = report_status

◆ VL53L1_RESULT_SIGMA_SD0

#define VL53L1_RESULT_SIGMA_SD0   0x0092

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['system_results', 'results']

fields:

  • [15:0] = result_sigma_sd0 (fixed point 14.2)

◆ VL53L1_RESULT_SIGMA_SD0_HI

#define VL53L1_RESULT_SIGMA_SD0_HI   0x0092

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_SIGMA_SD0_LO

#define VL53L1_RESULT_SIGMA_SD0_LO   0x0093

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_SIGMA_SD1

#define VL53L1_RESULT_SIGMA_SD1   0x00A6

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['system_results', 'results']

fields:

  • [15:0] = result_sigma_sd1 (fixed point 14.2)

◆ VL53L1_RESULT_SIGMA_SD1_HI

#define VL53L1_RESULT_SIGMA_SD1_HI   0x00A6

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_SIGMA_SD1_LO

#define VL53L1_RESULT_SIGMA_SD1_LO   0x00A7

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_SPARE_0_SD1

#define VL53L1_RESULT_SPARE_0_SD1   0x00AC

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['system_results', 'results']

fields:

  • [15:0] = result_spare_0_sd1

◆ VL53L1_RESULT_SPARE_0_SD1_HI

#define VL53L1_RESULT_SPARE_0_SD1_HI   0x00AC

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_SPARE_0_SD1_LO

#define VL53L1_RESULT_SPARE_0_SD1_LO   0x00AD

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_SPARE_1_SD1

#define VL53L1_RESULT_SPARE_1_SD1   0x00AE

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['system_results', 'results']

fields:

  • [15:0] = result_spare_1_sd1

◆ VL53L1_RESULT_SPARE_1_SD1_HI

#define VL53L1_RESULT_SPARE_1_SD1_HI   0x00AE

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_SPARE_1_SD1_LO

#define VL53L1_RESULT_SPARE_1_SD1_LO   0x00AF

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_SPARE_2_SD1

#define VL53L1_RESULT_SPARE_2_SD1   0x00B0

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['system_results', 'results']

fields:

  • [15:0] = result_spare_2_sd1

◆ VL53L1_RESULT_SPARE_2_SD1_HI

#define VL53L1_RESULT_SPARE_2_SD1_HI   0x00B0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_SPARE_2_SD1_LO

#define VL53L1_RESULT_SPARE_2_SD1_LO   0x00B1

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_RESULT_SPARE_3_SD1

#define VL53L1_RESULT_SPARE_3_SD1   0x00B2

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['system_results', 'results']

fields:

  • [7:0] = result_spare_3_sd1

◆ VL53L1_RESULT_STREAM_COUNT

#define VL53L1_RESULT_STREAM_COUNT   0x008B

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['system_results', 'results']

fields:

  • [7:0] = result_stream_count

◆ VL53L1_RESULT_THRESH_INFO

#define VL53L1_RESULT_THRESH_INFO   0x00B3

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['system_results', 'results']

fields:

  • [3:0] = result_distance_int_info
  • [7:4] = result_rate_int_info

◆ VL53L1_ROI_CONFIG_MODE_ROI_CENTRE_SPAD

#define VL53L1_ROI_CONFIG_MODE_ROI_CENTRE_SPAD   0x013E

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'roi_config']

fields:

  • [7:0] = mode_roi_center_spad

◆ VL53L1_ROI_CONFIG_MODE_ROI_XY_SIZE

#define VL53L1_ROI_CONFIG_MODE_ROI_XY_SIZE   0x013F

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['nvm_copy_data', 'roi_config']

fields:

  • [7:0] = mode_roi_xy_size

◆ VL53L1_ROI_CONFIG_USER_ROI_CENTRE_SPAD

#define VL53L1_ROI_CONFIG_USER_ROI_CENTRE_SPAD   0x007F

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['dynamic_config', 'gph_config']

fields:

  • [7:0] = user_roi_center_spad

◆ VL53L1_ROI_CONFIG_USER_ROI_REQUESTED_GLOBAL_XY_SIZE

#define VL53L1_ROI_CONFIG_USER_ROI_REQUESTED_GLOBAL_XY_SIZE   0x0080

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['dynamic_config', 'gph_config']

fields:

  • [7:0] = roi_config_user_roi_requested_global_xy_size

◆ VL53L1_SD_CONFIG_FIRST_ORDER_SELECT

#define VL53L1_SD_CONFIG_FIRST_ORDER_SELECT   0x007D

type: uint8_t
default: 0x00
info:

  • msb = 1
  • lsb = 0
  • i2c_size = 1

groups:
['dynamic_config', 'gph_config']

fields:

  • [0] = sd_config_first_order_select_rtn
  • [1] = sd_config_first_order_select_ref

◆ VL53L1_SD_CONFIG_INITIAL_PHASE_SD0

#define VL53L1_SD_CONFIG_INITIAL_PHASE_SD0   0x007A

type: uint8_t
default: 0x03
info:

  • msb = 6
  • lsb = 0
  • i2c_size = 1

groups:
['dynamic_config', 'gph_config']

fields:

  • [6:0] = sd_config_initial_phase_sd0

◆ VL53L1_SD_CONFIG_INITIAL_PHASE_SD1

#define VL53L1_SD_CONFIG_INITIAL_PHASE_SD1   0x007B

type: uint8_t
default: 0x03
info:

  • msb = 6
  • lsb = 0
  • i2c_size = 1

groups:
['dynamic_config', 'gph_config']

fields:

  • [6:0] = sd_config_initial_phase_sd1

◆ VL53L1_SD_CONFIG_QUANTIFIER

#define VL53L1_SD_CONFIG_QUANTIFIER   0x007E

type: uint8_t
default: 0x00
info:

  • msb = 3
  • lsb = 0
  • i2c_size = 1

groups:
['dynamic_config', 'gph_config']

fields:

  • [3:0] = sd_config_quantifier

◆ VL53L1_SD_CONFIG_RESET_STAGES_LSB

#define VL53L1_SD_CONFIG_RESET_STAGES_LSB   0x0043

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'sigmadelta_config']

fields:

  • [7:4] = accum_reset_clear_stage
  • [3:0] = count_reset_clear_stage

◆ VL53L1_SD_CONFIG_RESET_STAGES_MSB

#define VL53L1_SD_CONFIG_RESET_STAGES_MSB   0x0042

type: uint8_t
default: 0x00
info:

  • msb = 3
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'sigmadelta_config']

fields:

  • [3:0] = loop_init_clear_stage

◆ VL53L1_SD_CONFIG_WOI_SD0

#define VL53L1_SD_CONFIG_WOI_SD0   0x0078

type: uint8_t
default: 0x04
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['dynamic_config', 'gph_config']

fields:

  • [7:0] = sd_config_woi_sd0

◆ VL53L1_SD_CONFIG_WOI_SD1

#define VL53L1_SD_CONFIG_WOI_SD1   0x0079

type: uint8_t
default: 0x04
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['dynamic_config', 'gph_config']

fields:

  • [7:0] = sd_config_woi_sd1

◆ VL53L1_SHADOW_PHASECAL_RESULT_REFERENCE_PHASE_HI

#define VL53L1_SHADOW_PHASECAL_RESULT_REFERENCE_PHASE_HI   0x0FFE

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['shadow_system_results', 'histogram_results']

fields:

  • [7:0] = shadow_phasecal_result_reference_phase_hi

◆ VL53L1_SHADOW_PHASECAL_RESULT_REFERENCE_PHASE_LO

#define VL53L1_SHADOW_PHASECAL_RESULT_REFERENCE_PHASE_LO   0x0FFF

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['shadow_system_results', 'histogram_results']

fields:

  • [7:0] = shadow_phasecal_result_reference_phase_lo

◆ VL53L1_SHADOW_PHASECAL_RESULT_VCSEL_START

#define VL53L1_SHADOW_PHASECAL_RESULT_VCSEL_START   0x0FAE

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['shadow_system_results', 'histogram_results']

fields:

  • [7:0] = shadow_phasecal_result_vcsel_start

◆ VL53L1_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0

#define VL53L1_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0   0x0FB8

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['shadow_system_results', 'results']

fields:

  • [15:0] = shadow_result_ambient_count_rate_mcps_sd0 (fixed point 9.7)

◆ VL53L1_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0_HI

#define VL53L1_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0_HI   0x0FB8

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0_LO

#define VL53L1_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD0_LO   0x0FB9

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1

#define VL53L1_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1   0x0FCC

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['shadow_system_results', 'results']

fields:

  • [15:0] = shadow_result_ambient_count_rate_mcps_sd1 (fixed point 9.7)

◆ VL53L1_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1_HI

#define VL53L1_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1_HI   0x0FCC

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1_LO

#define VL53L1_SHADOW_RESULT_AMBIENT_COUNT_RATE_MCPS_SD1_LO   0x0FCD

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0

#define VL53L1_SHADOW_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0   0x0FC6

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['shadow_system_results', 'results']

fields:

  • [15:0] = shadow_result_avg_signal_count_rate_mcps_sd0 (fixed point 9.7)

◆ VL53L1_SHADOW_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI

#define VL53L1_SHADOW_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI   0x0FC6

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO

#define VL53L1_SHADOW_RESULT_AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO   0x0FC7

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0

#define VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0   0x0FDC

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['shadow_core_results', 'ranging_core_results']

fields:

  • [31:0] = shadow_result_core_ambient_window_events_sd0

◆ VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_0

#define VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_0   0x0FDF

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_1

#define VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_1   0x0FDE

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_2

#define VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_2   0x0FDD

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_3

#define VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD0_3   0x0FDC

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1

#define VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1   0x0FEC

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['shadow_core_results', 'ranging_core_results']

fields:

  • [31:0] = shadow_result_core_ambient_window_events_sd1

◆ VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_0

#define VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_0   0x0FEF

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_1

#define VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_1   0x0FEE

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_2

#define VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_2   0x0FED

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_3

#define VL53L1_SHADOW_RESULT_CORE_AMBIENT_WINDOW_EVENTS_SD1_3   0x0FEC

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0

#define VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0   0x0FE0

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['shadow_core_results', 'ranging_core_results']

fields:

  • [31:0] = shadow_result_core_ranging_total_events_sd0

◆ VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_0

#define VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_0   0x0FE3

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_1

#define VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_1   0x0FE2

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_2

#define VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_2   0x0FE1

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_3

#define VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD0_3   0x0FE0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1

#define VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1   0x0FF0

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['shadow_core_results', 'ranging_core_results']

fields:

  • [31:0] = shadow_result_core_ranging_total_events_sd1

◆ VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_0

#define VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_0   0x0FF3

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_1

#define VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_1   0x0FF2

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_2

#define VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_2   0x0FF1

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_3

#define VL53L1_SHADOW_RESULT_CORE_RANGING_TOTAL_EVENTS_SD1_3   0x0FF0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0

#define VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0   0x0FE4

type: int32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['shadow_core_results', 'ranging_core_results']

fields:

  • [31:0] = shadow_result_core_signal_total_events_sd0

◆ VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_0

#define VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_0   0x0FE7

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_1

#define VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_1   0x0FE6

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_2

#define VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_2   0x0FE5

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_3

#define VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD0_3   0x0FE4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1

#define VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1   0x0FF4

type: int32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['shadow_core_results', 'ranging_core_results']

fields:

  • [31:0] = shadow_result_core_signal_total_events_sd1

◆ VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_0

#define VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_0   0x0FF7

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_1

#define VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_1   0x0FF6

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_2

#define VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_2   0x0FF5

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_3

#define VL53L1_SHADOW_RESULT_CORE_SIGNAL_TOTAL_EVENTS_SD1_3   0x0FF4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_SPARE_0

#define VL53L1_SHADOW_RESULT_CORE_SPARE_0   0x0FFC

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['shadow_core_results', 'ranging_core_results']

fields:

  • [7:0] = shadow_result_core_spare_0

◆ VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0

#define VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0   0x0FE8

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['shadow_core_results', 'ranging_core_results']

fields:

  • [31:0] = shadow_result_core_total_periods_elapsed_sd0

◆ VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_0

#define VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_0   0x0FEB

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_1

#define VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_1   0x0FEA

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_2

#define VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_2   0x0FE9

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_3

#define VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD0_3   0x0FE8

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1

#define VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1   0x0FF8

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['shadow_core_results', 'ranging_core_results']

fields:

  • [31:0] = shadow_result_core_total_periods_elapsed_sd1

◆ VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_0

#define VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_0   0x0FFB

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_1

#define VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_1   0x0FFA

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_2

#define VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_2   0x0FF9

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_3

#define VL53L1_SHADOW_RESULT_CORE_TOTAL_PERIODS_ELAPSED_SD1_3   0x0FF8

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0

#define VL53L1_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0   0x0FB4

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['shadow_system_results', 'results']

fields:

  • [15:0] = shadow_result_dss_actual_effective_spads_sd0 (fixed point 8.8)

◆ VL53L1_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI

#define VL53L1_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI   0x0FB4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO

#define VL53L1_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO   0x0FB5

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1

#define VL53L1_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1   0x0FC8

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['shadow_system_results', 'results']

fields:

  • [15:0] = shadow_result_dss_actual_effective_spads_sd1 (fixed point 8.8)

◆ VL53L1_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI

#define VL53L1_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI   0x0FC8

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO

#define VL53L1_SHADOW_RESULT_DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO   0x0FC9

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0

#define VL53L1_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0   0x0FBE

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['shadow_system_results', 'results']

fields:

  • [15:0] = shadow_result_final_crosstalk_corrected_range_mm_sd0

◆ VL53L1_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI

#define VL53L1_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI   0x0FBE

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO

#define VL53L1_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO   0x0FBF

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1

#define VL53L1_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1   0x0FD2

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['shadow_system_results', 'results']

fields:

  • [15:0] = shadow_result_final_crosstalk_corrected_range_mm_sd1

◆ VL53L1_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI

#define VL53L1_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI   0x0FD2

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO

#define VL53L1_SHADOW_RESULT_FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO   0x0FD3

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_INTERRUPT_STATUS

#define VL53L1_SHADOW_RESULT_INTERRUPT_STATUS   0x0FB0

type: uint8_t
default: 0x00
info:

  • msb = 5
  • lsb = 0
  • i2c_size = 1

groups:
['shadow_system_results', 'results']

fields:

  • [2:0] = shadow_int_status
  • [4:3] = shadow_int_error_status
  • [5] = shadow_gph_id_gpio_status

◆ VL53L1_SHADOW_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0

#define VL53L1_SHADOW_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0   0x0FC2

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['shadow_system_results', 'results']

fields:

  • [15:0] = shadow_result_mm_inner_actual_effective_spads_sd0 (fixed point 8.8)

◆ VL53L1_SHADOW_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI

#define VL53L1_SHADOW_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI   0x0FC2

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO

#define VL53L1_SHADOW_RESULT_MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO   0x0FC3

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0

#define VL53L1_SHADOW_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0   0x0FC4

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['shadow_system_results', 'results']

fields:

  • [15:0] = shadow_result_mm_outer_actual_effective_spads_sd0 (fixed point 8.8)

◆ VL53L1_SHADOW_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI

#define VL53L1_SHADOW_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI   0x0FC4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO

#define VL53L1_SHADOW_RESULT_MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO   0x0FC5

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0

#define VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0   0x0FC0

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['shadow_system_results', 'results']

fields:

  • [15:0] = shadow_result_peak_signal_count_rate_crosstalk_corrected_mcps_sd0 (fixed point 9.7)

◆ VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI

#define VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI   0x0FC0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO

#define VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO   0x0FC1

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0

#define VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0   0x0FB6

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['shadow_system_results', 'results']

fields:

  • [15:0] = shadow_result_peak_signal_count_rate_mcps_sd0 (fixed point 9.7)

◆ VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI

#define VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI   0x0FB6

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO

#define VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO   0x0FB7

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1

#define VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1   0x0FCA

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['shadow_system_results', 'results']

fields:

  • [15:0] = shadow_result_peak_signal_count_rate_mcps_sd1 (fixed point 9.7)

◆ VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI

#define VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI   0x0FCA

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO

#define VL53L1_SHADOW_RESULT_PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO   0x0FCB

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_PHASE_SD0

#define VL53L1_SHADOW_RESULT_PHASE_SD0   0x0FBC

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['shadow_system_results', 'results']

fields:

  • [15:0] = shadow_result_phase_sd0 (fixed point 5.11)

◆ VL53L1_SHADOW_RESULT_PHASE_SD0_HI

#define VL53L1_SHADOW_RESULT_PHASE_SD0_HI   0x0FBC

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_PHASE_SD0_LO

#define VL53L1_SHADOW_RESULT_PHASE_SD0_LO   0x0FBD

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_PHASE_SD1

#define VL53L1_SHADOW_RESULT_PHASE_SD1   0x0FD0

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['shadow_system_results', 'results']

fields:

  • [15:0] = shadow_result_phase_sd1 (fixed point 5.11)

◆ VL53L1_SHADOW_RESULT_PHASE_SD1_HI

#define VL53L1_SHADOW_RESULT_PHASE_SD1_HI   0x0FD0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_PHASE_SD1_LO

#define VL53L1_SHADOW_RESULT_PHASE_SD1_LO   0x0FD1

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_RANGE_STATUS

#define VL53L1_SHADOW_RESULT_RANGE_STATUS   0x0FB1

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['shadow_system_results', 'results']

fields:

  • [4:0] = shadow_range_status
  • [5] = shadow_max_threshold_hit
  • [6] = shadow_min_threshold_hit
  • [7] = shadow_gph_id_range_status

◆ VL53L1_SHADOW_RESULT_REPORT_STATUS

#define VL53L1_SHADOW_RESULT_REPORT_STATUS   0x0FB2

type: uint8_t
default: 0x00
info:

  • msb = 3
  • lsb = 0
  • i2c_size = 1

groups:
['shadow_system_results', 'results']

fields:

  • [3:0] = shadow_report_status

◆ VL53L1_SHADOW_RESULT_SIGMA_SD0

#define VL53L1_SHADOW_RESULT_SIGMA_SD0   0x0FBA

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['shadow_system_results', 'results']

fields:

  • [15:0] = shadow_result_sigma_sd0 (fixed point 14.2)

◆ VL53L1_SHADOW_RESULT_SIGMA_SD0_HI

#define VL53L1_SHADOW_RESULT_SIGMA_SD0_HI   0x0FBA

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_SIGMA_SD0_LO

#define VL53L1_SHADOW_RESULT_SIGMA_SD0_LO   0x0FBB

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_SIGMA_SD1

#define VL53L1_SHADOW_RESULT_SIGMA_SD1   0x0FCE

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['shadow_system_results', 'results']

fields:

  • [15:0] = shadow_result_sigma_sd1 (fixed point 14.2)

◆ VL53L1_SHADOW_RESULT_SIGMA_SD1_HI

#define VL53L1_SHADOW_RESULT_SIGMA_SD1_HI   0x0FCE

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_SIGMA_SD1_LO

#define VL53L1_SHADOW_RESULT_SIGMA_SD1_LO   0x0FCF

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_SPARE_0_SD1

#define VL53L1_SHADOW_RESULT_SPARE_0_SD1   0x0FD4

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['shadow_system_results', 'results']

fields:

  • [15:0] = shadow_result_spare_0_sd1

◆ VL53L1_SHADOW_RESULT_SPARE_0_SD1_HI

#define VL53L1_SHADOW_RESULT_SPARE_0_SD1_HI   0x0FD4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_SPARE_0_SD1_LO

#define VL53L1_SHADOW_RESULT_SPARE_0_SD1_LO   0x0FD5

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_SPARE_1_SD1

#define VL53L1_SHADOW_RESULT_SPARE_1_SD1   0x0FD6

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['shadow_system_results', 'results']

fields:

  • [15:0] = shadow_result_spare_1_sd1

◆ VL53L1_SHADOW_RESULT_SPARE_1_SD1_HI

#define VL53L1_SHADOW_RESULT_SPARE_1_SD1_HI   0x0FD6

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_SPARE_1_SD1_LO

#define VL53L1_SHADOW_RESULT_SPARE_1_SD1_LO   0x0FD7

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_SPARE_2_SD1

#define VL53L1_SHADOW_RESULT_SPARE_2_SD1   0x0FD8

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['shadow_system_results', 'results']

fields:

  • [15:0] = shadow_result_spare_2_sd1

◆ VL53L1_SHADOW_RESULT_SPARE_2_SD1_HI

#define VL53L1_SHADOW_RESULT_SPARE_2_SD1_HI   0x0FD8

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_SPARE_2_SD1_LO

#define VL53L1_SHADOW_RESULT_SPARE_2_SD1_LO   0x0FD9

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SHADOW_RESULT_SPARE_3_SD1

#define VL53L1_SHADOW_RESULT_SPARE_3_SD1   0x0FDA

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['shadow_system_results', 'results']

fields:

  • [7:0] = shadow_result_spare_3_sd1

◆ VL53L1_SHADOW_RESULT_STREAM_COUNT

#define VL53L1_SHADOW_RESULT_STREAM_COUNT   0x0FB3

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['shadow_system_results', 'results']

fields:

  • [7:0] = shadow_result_stream_count

◆ VL53L1_SHADOW_RESULT_THRESH_INFO

#define VL53L1_SHADOW_RESULT_THRESH_INFO   0x0FDB

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['shadow_system_results', 'results']

fields:

  • [3:0] = shadow_result_distance_int_info
  • [7:4] = shadow_result_rate_int_info

◆ VL53L1_SIGMA_ESTIMATOR_CALC_SPARE_0

#define VL53L1_SIGMA_ESTIMATOR_CALC_SPARE_0   0x0F80

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['patch_results', 'sigma_est_spare']

fields:

  • [7:0] = sigma_estimator_calc_spare_0

◆ VL53L1_SIGMA_ESTIMATOR_EFFECTIVE_AMBIENT_WIDTH_NS

#define VL53L1_SIGMA_ESTIMATOR_EFFECTIVE_AMBIENT_WIDTH_NS   0x0037

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'algo_config']

fields:

  • [7:0] = sigma_estimator_eff_ambient_width

◆ VL53L1_SIGMA_ESTIMATOR_EFFECTIVE_PULSE_WIDTH_NS

#define VL53L1_SIGMA_ESTIMATOR_EFFECTIVE_PULSE_WIDTH_NS   0x0036

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'algo_config']

fields:

  • [7:0] = sigma_estimator_eff_pulse_width

◆ VL53L1_SIGMA_ESTIMATOR_SIGMA_REF_MM

#define VL53L1_SIGMA_ESTIMATOR_SIGMA_REF_MM   0x0038

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'algo_config']

fields:

  • [7:0] = sigma_estimator_sigma_ref

◆ VL53L1_SOFT_RESET

#define VL53L1_SOFT_RESET   0x0000

VL53L1 Register Map definitions.

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SOFT_RESET_GO1

#define VL53L1_SOFT_RESET_GO1   0x0B00

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SPARE_HOST_CONFIG_STATIC_CONFIG_SPARE_0

#define VL53L1_SPARE_HOST_CONFIG_STATIC_CONFIG_SPARE_0   0x003A

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'algo_config']

fields:

  • [7:0] = static_config_spare_0

◆ VL53L1_SPARE_HOST_CONFIG_STATIC_CONFIG_SPARE_1

#define VL53L1_SPARE_HOST_CONFIG_STATIC_CONFIG_SPARE_1   0x003B

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'algo_config']

fields:

  • [7:0] = static_config_spare_1

◆ VL53L1_SPARE_HOST_CONFIG_STATIC_CONFIG_SPARE_2

#define VL53L1_SPARE_HOST_CONFIG_STATIC_CONFIG_SPARE_2   0x0041

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'algo_config']

fields:

  • [7:0] = static_config_spare_2

◆ VL53L1_SPI_ASYNC_MUX_CTRL

#define VL53L1_SPI_ASYNC_MUX_CTRL   0x04C0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SYSTEM_ENABLE_XTALK_PER_QUADRANT

#define VL53L1_SYSTEM_ENABLE_XTALK_PER_QUADRANT   0x0076

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['dynamic_config', 'gph_config']

fields:

  • [0] = system_enable_xtalk_per_quadrant

◆ VL53L1_SYSTEM_FRACTIONAL_ENABLE

#define VL53L1_SYSTEM_FRACTIONAL_ENABLE   0x0070

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['timing_config', 'system_config']

fields:

  • [0] = range_fractional_enable

◆ VL53L1_SYSTEM_GROUPED_PARAMETER_HOLD

#define VL53L1_SYSTEM_GROUPED_PARAMETER_HOLD   0x0082

type: uint8_t
default: 0x00
info:

  • msb = 1
  • lsb = 0
  • i2c_size = 1

groups:
['dynamic_config', 'gph_config']

fields:

  • [0] = grouped_parameter_hold
  • [1] = grouped_parameter_hold_id

◆ VL53L1_SYSTEM_GROUPED_PARAMETER_HOLD_0

#define VL53L1_SYSTEM_GROUPED_PARAMETER_HOLD_0   0x0071

type: uint8_t
default: 0x00
info:

  • msb = 1
  • lsb = 0
  • i2c_size = 1

groups:
['dynamic_config', 'gph_config']

fields:

  • [0] = grouped_parameter_hold
  • [1] = grouped_parameter_hold_id

◆ VL53L1_SYSTEM_GROUPED_PARAMETER_HOLD_1

#define VL53L1_SYSTEM_GROUPED_PARAMETER_HOLD_1   0x007C

type: uint8_t
default: 0x00
info:

  • msb = 1
  • lsb = 0
  • i2c_size = 1

groups:
['dynamic_config', 'gph_config']

fields:

  • [0] = grouped_parameter_hold
  • [1] = grouped_parameter_hold_id

◆ VL53L1_SYSTEM_INTERMEASUREMENT_PERIOD

#define VL53L1_SYSTEM_INTERMEASUREMENT_PERIOD   0x006C

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['timing_config', 'system_config']

fields:

  • [31:0] = intermeasurement_period

◆ VL53L1_SYSTEM_INTERMEASUREMENT_PERIOD_0

#define VL53L1_SYSTEM_INTERMEASUREMENT_PERIOD_0   0x006F

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SYSTEM_INTERMEASUREMENT_PERIOD_1

#define VL53L1_SYSTEM_INTERMEASUREMENT_PERIOD_1   0x006E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SYSTEM_INTERMEASUREMENT_PERIOD_2

#define VL53L1_SYSTEM_INTERMEASUREMENT_PERIOD_2   0x006D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SYSTEM_INTERMEASUREMENT_PERIOD_3

#define VL53L1_SYSTEM_INTERMEASUREMENT_PERIOD_3   0x006C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SYSTEM_INTERRUPT_CLEAR

#define VL53L1_SYSTEM_INTERRUPT_CLEAR   0x0086

type: uint8_t
default: 0x00
info:

  • msb = 1
  • lsb = 0
  • i2c_size = 1

groups:
['system_control', 'system_int_clr']

fields:

  • [0] = sys_interrupt_clear_range
  • [1] = sys_interrupt_clear_error

◆ VL53L1_SYSTEM_INTERRUPT_CONFIG_GPIO

#define VL53L1_SYSTEM_INTERRUPT_CONFIG_GPIO   0x0046

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['general_config', 'gph_config']

fields:

  • [1:0] = int_mode_distance
  • [3:2] = int_mode_rate
  • [4] = int_spare
  • [5] = int_new_measure_ready
  • [6] = int_no_target_en
  • [7] = int_combined_mode

◆ VL53L1_SYSTEM_INTERRUPT_SET

#define VL53L1_SYSTEM_INTERRUPT_SET   0x00FC

type: uint8_t
default: 0x00
info:

  • msb = 1
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'system_int_set']

fields:

  • [0] = sys_interrupt_set_range
  • [1] = sys_interrupt_set_error

◆ VL53L1_SYSTEM_MODE_START

#define VL53L1_SYSTEM_MODE_START   0x0087

type: uint8_t
default: 0x00
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['system_control', 'system_start']

fields:

  • [1:0] = scheduler_mode
  • [3:2] = readout_mode
  • [4] = mode_range_single_shot
  • [5] = mode_range_back_to_back
  • [6] = mode_range_timed
  • [7] = mode_range_abort

◆ VL53L1_SYSTEM_SEED_CONFIG

#define VL53L1_SYSTEM_SEED_CONFIG   0x0077

type: uint8_t
default: 0x00
info:

  • msb = 2
  • lsb = 0
  • i2c_size = 1

groups:
['dynamic_config', 'gph_config']

fields:

  • [1:0] = system_seed_config
  • [2] = system_fw_pause_ctrl

◆ VL53L1_SYSTEM_SEQUENCE_CONFIG

#define VL53L1_SYSTEM_SEQUENCE_CONFIG   0x0081

type: uint8_t
default: 0xFF
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['dynamic_config', 'gph_config']

fields:

  • [0] = sequence_vhv_en
  • [1] = sequence_phasecal_en
  • [2] = sequence_reference_phase_en
  • [3] = sequence_dss1_en
  • [4] = sequence_dss2_en
  • [5] = sequence_mm1_en
  • [6] = sequence_mm2_en
  • [7] = sequence_range_en

◆ VL53L1_SYSTEM_STREAM_COUNT_CTRL

#define VL53L1_SYSTEM_STREAM_COUNT_CTRL   0x0084

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['system_control', 'stream_ctrl']

fields:

  • [0] = retain_stream_count

◆ VL53L1_SYSTEM_THRESH_HIGH

#define VL53L1_SYSTEM_THRESH_HIGH   0x0072

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['dynamic_config', 'gph_config']

fields:

  • [15:0] = thresh_high

◆ VL53L1_SYSTEM_THRESH_HIGH_HI

#define VL53L1_SYSTEM_THRESH_HIGH_HI   0x0072

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SYSTEM_THRESH_HIGH_LO

#define VL53L1_SYSTEM_THRESH_HIGH_LO   0x0073

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SYSTEM_THRESH_LOW

#define VL53L1_SYSTEM_THRESH_LOW   0x0074

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['dynamic_config', 'gph_config']

fields:

  • [15:0] = thresh_low

◆ VL53L1_SYSTEM_THRESH_LOW_HI

#define VL53L1_SYSTEM_THRESH_LOW_HI   0x0074

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SYSTEM_THRESH_LOW_LO

#define VL53L1_SYSTEM_THRESH_LOW_LO   0x0075

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SYSTEM_THRESH_RATE_HIGH

#define VL53L1_SYSTEM_THRESH_RATE_HIGH   0x0050

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['general_config', 'gph_config']

fields:

  • [15:0] = thresh_rate_high (fixed point 9.7)

◆ VL53L1_SYSTEM_THRESH_RATE_HIGH_HI

#define VL53L1_SYSTEM_THRESH_RATE_HIGH_HI   0x0050

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SYSTEM_THRESH_RATE_HIGH_LO

#define VL53L1_SYSTEM_THRESH_RATE_HIGH_LO   0x0051

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SYSTEM_THRESH_RATE_LOW

#define VL53L1_SYSTEM_THRESH_RATE_LOW   0x0052

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['general_config', 'gph_config']

fields:

  • [15:0] = thresh_rate_low (fixed point 9.7)

◆ VL53L1_SYSTEM_THRESH_RATE_LOW_HI

#define VL53L1_SYSTEM_THRESH_RATE_LOW_HI   0x0052

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_SYSTEM_THRESH_RATE_LOW_LO

#define VL53L1_SYSTEM_THRESH_RATE_LOW_LO   0x0053

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TEST_BIST_RAM_CTRL

#define VL53L1_TEST_BIST_RAM_CTRL   0x04E4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TEST_BIST_RAM_RESULT

#define VL53L1_TEST_BIST_RAM_RESULT   0x04E5

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TEST_BIST_ROM_CTRL

#define VL53L1_TEST_BIST_ROM_CTRL   0x04E0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TEST_BIST_ROM_MCU_SIG

#define VL53L1_TEST_BIST_ROM_MCU_SIG   0x04E2

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TEST_BIST_ROM_MCU_SIG_HI

#define VL53L1_TEST_BIST_ROM_MCU_SIG_HI   0x04E2

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TEST_BIST_ROM_MCU_SIG_LO

#define VL53L1_TEST_BIST_ROM_MCU_SIG_LO   0x04E3

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TEST_BIST_ROM_RESULT

#define VL53L1_TEST_BIST_ROM_RESULT   0x04E1

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TEST_MODE_CTRL

#define VL53L1_TEST_MODE_CTRL   0x0027

type: uint8_t
default: 0x00
info:

  • msb = 3
  • lsb = 0
  • i2c_size = 1

groups:
['static_config', 'test_mode_config']

fields:

  • [3:0] = test_mode_cmd

◆ VL53L1_TEST_MODE_STATUS

#define VL53L1_TEST_MODE_STATUS   0x00E4

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'test_mode_status']

fields:

  • [0] = test_mode_status

◆ VL53L1_TEST_PLL_BIST_COUNT_OUT

#define VL53L1_TEST_PLL_BIST_COUNT_OUT   0x04F4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TEST_PLL_BIST_COUNT_OUT_HI

#define VL53L1_TEST_PLL_BIST_COUNT_OUT_HI   0x04F4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TEST_PLL_BIST_COUNT_OUT_LO

#define VL53L1_TEST_PLL_BIST_COUNT_OUT_LO   0x04F5

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TEST_PLL_BIST_CTRL

#define VL53L1_TEST_PLL_BIST_CTRL   0x04F7

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TEST_PLL_BIST_GONOGO

#define VL53L1_TEST_PLL_BIST_GONOGO   0x04F6

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TEST_PLL_BIST_MAX_THRESHOLD

#define VL53L1_TEST_PLL_BIST_MAX_THRESHOLD   0x04F2

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TEST_PLL_BIST_MAX_THRESHOLD_HI

#define VL53L1_TEST_PLL_BIST_MAX_THRESHOLD_HI   0x04F2

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TEST_PLL_BIST_MAX_THRESHOLD_LO

#define VL53L1_TEST_PLL_BIST_MAX_THRESHOLD_LO   0x04F3

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TEST_PLL_BIST_MIN_THRESHOLD

#define VL53L1_TEST_PLL_BIST_MIN_THRESHOLD   0x04F0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TEST_PLL_BIST_MIN_THRESHOLD_HI

#define VL53L1_TEST_PLL_BIST_MIN_THRESHOLD_HI   0x04F0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TEST_PLL_BIST_MIN_THRESHOLD_LO

#define VL53L1_TEST_PLL_BIST_MIN_THRESHOLD_LO   0x04F1

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TEST_TMC

#define VL53L1_TEST_TMC   0x04E8

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TIMER0_CTRL

#define VL53L1_TIMER0_CTRL   0x0428

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TIMER0_VALUE_IN

#define VL53L1_TIMER0_VALUE_IN   0x0420

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TIMER0_VALUE_IN_0

#define VL53L1_TIMER0_VALUE_IN_0   0x0423

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TIMER0_VALUE_IN_1

#define VL53L1_TIMER0_VALUE_IN_1   0x0422

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TIMER0_VALUE_IN_2

#define VL53L1_TIMER0_VALUE_IN_2   0x0421

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TIMER0_VALUE_IN_3

#define VL53L1_TIMER0_VALUE_IN_3   0x0420

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TIMER1_CTRL

#define VL53L1_TIMER1_CTRL   0x0429

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TIMER1_VALUE_IN

#define VL53L1_TIMER1_VALUE_IN   0x0424

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TIMER1_VALUE_IN_0

#define VL53L1_TIMER1_VALUE_IN_0   0x0427

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TIMER1_VALUE_IN_1

#define VL53L1_TIMER1_VALUE_IN_1   0x0426

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TIMER1_VALUE_IN_2

#define VL53L1_TIMER1_VALUE_IN_2   0x0425

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_TIMER1_VALUE_IN_3

#define VL53L1_TIMER1_VALUE_IN_3   0x0424

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_VHV_CONFIG_COUNT_THRESH

#define VL53L1_VHV_CONFIG_COUNT_THRESH   0x0009

type: uint8_t
default: 0x80
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['static_nvm_managed', 'vhv_config']

fields:

  • [7:0] = vhv_count_thresh

◆ VL53L1_VHV_CONFIG_INIT

#define VL53L1_VHV_CONFIG_INIT   0x000B

type: uint8_t
default: 0x20
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['static_nvm_managed', 'vhv_config']

fields:

  • [7] = vhv0_init_enable
  • [5:0] = vhv0_init_value

◆ VL53L1_VHV_CONFIG_OFFSET

#define VL53L1_VHV_CONFIG_OFFSET   0x000A

type: uint8_t
default: 0x07
info:

  • msb = 5
  • lsb = 0
  • i2c_size = 1

groups:
['static_nvm_managed', 'vhv_config']

fields:

  • [5:0] = vhv_step_val

◆ VL53L1_VHV_CONFIG_TIMEOUT_MACROP_LOOP_BOUND

#define VL53L1_VHV_CONFIG_TIMEOUT_MACROP_LOOP_BOUND   0x0008

type: uint8_t
default: 0x81
info:

  • msb = 7
  • lsb = 0
  • i2c_size = 1

groups:
['static_nvm_managed', 'vhv_config']

fields:

  • [1:0] = vhv_timeout_macrop
  • [7:2] = vhv_loop_bound

◆ VL53L1_VHV_RESULT_COLDBOOT_STATUS

#define VL53L1_VHV_RESULT_COLDBOOT_STATUS   0x00DB

type: uint8_t
default: 0x00
info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'vhv_results']

fields:

  • [0] = vhv_result_coldboot_status

◆ VL53L1_VHV_RESULT_LATEST_SETTING

#define VL53L1_VHV_RESULT_LATEST_SETTING   0x00DD

type: uint8_t
default: 0x00
info:

  • msb = 5
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'vhv_results']

fields:

  • [5:0] = cp_sel_latest_setting

◆ VL53L1_VHV_RESULT_PEAK_SIGNAL_RATE_MCPS

#define VL53L1_VHV_RESULT_PEAK_SIGNAL_RATE_MCPS   0x0F82

type: uint16_t
default: 0x0000
info:

  • msb = 15
  • lsb = 0
  • i2c_size = 2

groups:
['patch_results', 'vhv_results']

fields:

  • [15:0] = vhv_result_peak_signal_rate_mcps

◆ VL53L1_VHV_RESULT_PEAK_SIGNAL_RATE_MCPS_HI

#define VL53L1_VHV_RESULT_PEAK_SIGNAL_RATE_MCPS_HI   0x0F82

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_VHV_RESULT_PEAK_SIGNAL_RATE_MCPS_LO

#define VL53L1_VHV_RESULT_PEAK_SIGNAL_RATE_MCPS_LO   0x0F83

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_VHV_RESULT_SEARCH_RESULT

#define VL53L1_VHV_RESULT_SEARCH_RESULT   0x00DC

type: uint8_t
default: 0x00
info:

  • msb = 5
  • lsb = 0
  • i2c_size = 1

groups:
['debug_results', 'vhv_results']

fields:

  • [5:0] = cp_sel_result

◆ VL53L1_VHV_RESULT_SIGNAL_TOTAL_EVENTS_REF

#define VL53L1_VHV_RESULT_SIGNAL_TOTAL_EVENTS_REF   0x0F84

type: uint32_t
default: 0x00000000
info:

  • msb = 31
  • lsb = 0
  • i2c_size = 4

groups:
['patch_results', 'vhv_results']

fields:

  • [31:0] = vhv_result_signal_total_events_ref

◆ VL53L1_VHV_RESULT_SIGNAL_TOTAL_EVENTS_REF_0

#define VL53L1_VHV_RESULT_SIGNAL_TOTAL_EVENTS_REF_0   0x0F87

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_VHV_RESULT_SIGNAL_TOTAL_EVENTS_REF_1

#define VL53L1_VHV_RESULT_SIGNAL_TOTAL_EVENTS_REF_1   0x0F86

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_VHV_RESULT_SIGNAL_TOTAL_EVENTS_REF_2

#define VL53L1_VHV_RESULT_SIGNAL_TOTAL_EVENTS_REF_2   0x0F85

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_VHV_RESULT_SIGNAL_TOTAL_EVENTS_REF_3

#define VL53L1_VHV_RESULT_SIGNAL_TOTAL_EVENTS_REF_3   0x0F84

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_XTALK_CALC_XTALK_FOR_ENABLED_SPADS

#define VL53L1_XTALK_CALC_XTALK_FOR_ENABLED_SPADS   0x0F98

type: uint32_t
default: 0x00000000
info:

  • msb = 23
  • lsb = 0
  • i2c_size = 4

groups:
['patch_results', 'xtalk_calc']

fields:

  • [23:0] = xtalk_calc_xtalk_for_enabled_spads (fixed point 11.13)

◆ VL53L1_XTALK_CALC_XTALK_FOR_ENABLED_SPADS_0

#define VL53L1_XTALK_CALC_XTALK_FOR_ENABLED_SPADS_0   0x0F9B

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_XTALK_CALC_XTALK_FOR_ENABLED_SPADS_1

#define VL53L1_XTALK_CALC_XTALK_FOR_ENABLED_SPADS_1   0x0F9A

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_XTALK_CALC_XTALK_FOR_ENABLED_SPADS_2

#define VL53L1_XTALK_CALC_XTALK_FOR_ENABLED_SPADS_2   0x0F99

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_XTALK_CALC_XTALK_FOR_ENABLED_SPADS_3

#define VL53L1_XTALK_CALC_XTALK_FOR_ENABLED_SPADS_3   0x0F98

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_XTALK_RESULT_AVG_XTALK_MM_INNER_ROI_KCPS

#define VL53L1_XTALK_RESULT_AVG_XTALK_MM_INNER_ROI_KCPS   0x0FA0

type: uint32_t
default: 0x00000000
info:

  • msb = 23
  • lsb = 0
  • i2c_size = 4

groups:
['patch_results', 'xtalk_results']

fields:

  • [23:0] = xtalk_result_avg_xtalk_mm_inner_roi_kcps (fixed point 11.13)

◆ VL53L1_XTALK_RESULT_AVG_XTALK_MM_INNER_ROI_KCPS_0

#define VL53L1_XTALK_RESULT_AVG_XTALK_MM_INNER_ROI_KCPS_0   0x0FA3

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_XTALK_RESULT_AVG_XTALK_MM_INNER_ROI_KCPS_1

#define VL53L1_XTALK_RESULT_AVG_XTALK_MM_INNER_ROI_KCPS_1   0x0FA2

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_XTALK_RESULT_AVG_XTALK_MM_INNER_ROI_KCPS_2

#define VL53L1_XTALK_RESULT_AVG_XTALK_MM_INNER_ROI_KCPS_2   0x0FA1

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_XTALK_RESULT_AVG_XTALK_MM_INNER_ROI_KCPS_3

#define VL53L1_XTALK_RESULT_AVG_XTALK_MM_INNER_ROI_KCPS_3   0x0FA0

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_XTALK_RESULT_AVG_XTALK_MM_OUTER_ROI_KCPS

#define VL53L1_XTALK_RESULT_AVG_XTALK_MM_OUTER_ROI_KCPS   0x0FA4

type: uint32_t
default: 0x00000000
info:

  • msb = 23
  • lsb = 0
  • i2c_size = 4

groups:
['patch_results', 'xtalk_results']

fields:

  • [23:0] = xtalk_result_avg_xtalk_mm_outer_roi_kcps (fixed point 11.13)

◆ VL53L1_XTALK_RESULT_AVG_XTALK_MM_OUTER_ROI_KCPS_0

#define VL53L1_XTALK_RESULT_AVG_XTALK_MM_OUTER_ROI_KCPS_0   0x0FA7

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_XTALK_RESULT_AVG_XTALK_MM_OUTER_ROI_KCPS_1

#define VL53L1_XTALK_RESULT_AVG_XTALK_MM_OUTER_ROI_KCPS_1   0x0FA6

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_XTALK_RESULT_AVG_XTALK_MM_OUTER_ROI_KCPS_2

#define VL53L1_XTALK_RESULT_AVG_XTALK_MM_OUTER_ROI_KCPS_2   0x0FA5

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_XTALK_RESULT_AVG_XTALK_MM_OUTER_ROI_KCPS_3

#define VL53L1_XTALK_RESULT_AVG_XTALK_MM_OUTER_ROI_KCPS_3   0x0FA4

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_XTALK_RESULT_AVG_XTALK_USER_ROI_KCPS

#define VL53L1_XTALK_RESULT_AVG_XTALK_USER_ROI_KCPS   0x0F9C

type: uint32_t
default: 0x00000000
info:

  • msb = 23
  • lsb = 0
  • i2c_size = 4

groups:
['patch_results', 'xtalk_results']

fields:

  • [23:0] = xtalk_result_avg_xtalk_user_roi_kcps (fixed point 11.13)

◆ VL53L1_XTALK_RESULT_AVG_XTALK_USER_ROI_KCPS_0

#define VL53L1_XTALK_RESULT_AVG_XTALK_USER_ROI_KCPS_0   0x0F9F

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_XTALK_RESULT_AVG_XTALK_USER_ROI_KCPS_1

#define VL53L1_XTALK_RESULT_AVG_XTALK_USER_ROI_KCPS_1   0x0F9E

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_XTALK_RESULT_AVG_XTALK_USER_ROI_KCPS_2

#define VL53L1_XTALK_RESULT_AVG_XTALK_USER_ROI_KCPS_2   0x0F9D

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1

◆ VL53L1_XTALK_RESULT_AVG_XTALK_USER_ROI_KCPS_3

#define VL53L1_XTALK_RESULT_AVG_XTALK_USER_ROI_KCPS_3   0x0F9C

info:

  • msb = 0
  • lsb = 0
  • i2c_size = 1
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